Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8169236 | Frequency detection mechanism for a clock generation circuit A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency mul... | 05/01/2012 |
| 8125250 | Frequency detection mechanism for a clock generation circuit A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency mul... | 02/28/2012 |
| 7852122 | Transmission circuit for transmitting a differential signal having pulse time larger than a predetermined minimum pulse time and CMOS semiconductor device A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a potential difference between two transmission lines; a driven unit for o... | 12/14/2010 |
| 7696789 | High-frequency signal detector Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential ... | 04/13/2010 |
| 7511537 | Comparator circuit for reducing current consumption by suppressing glitches during a transitional period A comparator circuit for reducing current consumption in a low consumption mode while suppressing the generation of glitches during a transitional period. The comparator circuit includes a comparison core circuit unit, a monitor circuit unit formed by a first transi... | 03/31/2009 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7388408 | Phase-frequency detector capable of reducing dead zone A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sens... | 06/17/2008 |
| 7375557 | Phase-locked loop and method thereof and a phase-frequency detector and method thereof The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a del... | 05/20/2008 |
| 7370247 | Dynamic offset compensation based on false transitions A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detec... | 05/06/2008 |
| 7242223 | Clock frequency monitor A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given ... | 07/10/2007 |
| 7236551 | Linear half-rate phase detector for clock recovery and method therefor There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and... | 06/26/2007 |
| 7231009 | Data synchronization across an asynchronous boundary using, for example, multi-phase clocks Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determi... | 06/12/2007 |
| 7218157 | Phase locked loop A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means... | 05/15/2007 |
| 7200794 | Method and system for adaptive interleaving A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmiss... | 04/03/2007 |
| 7181205 | I/Q calibration The amplitude and phase errors of the modulation and demodulation in a transceiver are corrected by a self-calibration procedure in which a test signal is applied to the baseband input of the transmitter, and the output of the modulator is looped back to the input o... | 02/20/2007 |
| 7136771 | Semiconductor device and testing circuit which can carries out a verifying test effectively for non-volatile memory cells A testing circuit includes m block test units and a first logical processing unit. The block test unit compares a first data outputted from a test object with a reference data, and outputs a result as a test circuit output signal based on a output control signal. Th... | 11/14/2006 |
| 7112959 | Comparator circuit and rotation detector The comparator circuit includes an amplifier amplifying a voltage signal inputted from outside, a voltage dividing circuit dividing down a power supply voltage supplied from outside, thereby producing a reference voltage, a waveform dull circuit dulling the referenc... | 09/26/2006 |
| 7102398 | Circuit for two PLLs for horizontal deflection A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output signal. A first PLL circuit is arranged to provide equalizing pulse remov... | 09/05/2006 |
| 7095254 | Method for producing a control signal which indicates a frequency error A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies... | 08/22/2006 |
| 7061277 | Low power differential-to-single-ended converter with good duty cycle performance A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive diffe... | 06/13/2006 |
| 7057419 | Phase synchronization circuit In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comp... | 06/06/2006 |
| 7038497 | Differential current mode phase/frequency detector circuit A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be... | 05/02/2006 |
| 6998886 | Apparatus and method for PLL with equalizing pulse removal A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circ... | 02/14/2006 |
| 6995607 | Low-pass filter and feedback system In a low-pass filter, the filter characteristics equivalent to those of a conventional low-pass filter are maintained, the size of a capacitive element is decreased, and the low-pass filter operates stably. Further, a MOS capacitor is used as a capacitive element. F... | 02/07/2006 |
| 6982592 | Zero if complex quadrature frequency discriminator and FM demodulator A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for hig... | 01/03/2006 |
| 6949958 | Phase comparator capable of tolerating a non-50% duty-cycle clocks A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 09/27/2005 |
| 6944569 | Method and apparatus for generating an electronic test signal The present invention relates to a method and an apparatus for generating an electronic test signal, and particularly to the use of such a method and apparatus for calibrating meters used to measure electrical characteristics such as voltage, current, phase angle an... | 09/13/2005 |
| 6847255 | Zero IF complex quadrature frequency discriminator and FM demodulator A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for hig... | 01/25/2005 |
| 6842049 | Method of and apparatus for detecting difference between the frequencies, and phase locked loop circuit An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequ... | 01/11/2005 |
| 6750682 | Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequ... | 06/15/2004 |
| 6665367 | Embedded frequency counter with flexible configuration An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit ... | 12/16/2003 |
| 6642747 | Frequency detector for a phase locked loop system A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged t... | 11/04/2003 |
| 6580297 | Frequency comparison circuit The objective of the invention is to provide technology to give high-speed DVD RF signal reading. Frequency comparison circuit 1 of the present invention has edge spacing detection circuit 3, maximum spacing detection circuit 4, and minimum spacing detect... | 06/17/2003 |
| 6563346 | Phase independent frequency comparator A method and circuit for comparing the frequencies of two clocks (clock-- 1 and clock-- 2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized... | 05/13/2003 |
| 6448820 | Fast locking phase frequency detector A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit... | 09/10/2002 |
| 6407642 | Frequency detector and phase-locked loop circuit including the detector A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive ... | 06/18/2002 |
| 6359948 | Phase-locked loop circuit with reduced jitter An improved phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency d... | 03/19/2002 |
| 6333646 | Abnormal clock detector and abnormal clock detecting apparatus Frequencies of clocks CLK1 and CLK2 are divided in frequency divider circuits (11 to 14), frequency-divided clocks CLK1A and CLK1B are input into clock comparators (15) and (16). Frequency-divided clocks CLK2A and CLK2B are input into clock comparators (1... | 12/25/2001 |
| 6326826 | Wide frequency-range delay-locked loop circuit A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the mult... | 12/04/2001 |
| 6269136 | Digital differential analyzer data synchronizer A digital differential analyzer data synchronizer receives data at a first clock rate and synchronizes the data to a second clock rate. The two clock rates are related by a ratio of two integers, but have a variable phase relationship. The synchronizer pl... | 07/31/2001 |
