Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 8125249 | Frequency measuring circuit and semiconductor device having the same A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides ... | 02/28/2012 |
| 7843228 | Half bin linear frequency discriminator Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin fre... | 11/30/2010 |
| 7795928 | Circuit for matching semiconductor device behavior A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub... | 09/14/2010 |
| 7528632 | Half bin linear frequency discriminator Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin fre... | 05/05/2009 |
| 7427879 | Frequency detector utilizing pulse generator, and method thereof The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock f... | 09/23/2008 |
| 7401306 | Apparatus and method for verification support, and computer product A verification support apparatus verifies an object. The object includes a plurality of clock domains and each clock domain includes a plurality of registers. The verification support apparatus includes an input receiving unit that receives logical circuit descripti... | 07/15/2008 |
| 7382165 | Method for matching semiconductor device behavior A selection circuit and method. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a g... | 06/03/2008 |
| 7378880 | Frequency comparator A frequency comparator comparing frequencies of a first clock signal and a reference clock signal. The frequency comparator includes a phase-frequency detector and a comparison module. The phase-frequency detector receives the first clock signal and the reference cl... | 05/27/2008 |
| 7337356 | Systematic and random error detection and recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e... | 02/26/2008 |
| 7334199 | System and method for breaking a feedback loop using a voltage controlled voltage source terminated subnetwork model A system and method is disclosed for breaking a feedback loop by replacing at least one component in the feedback loop with a model containing two physically disconnected subnetworks that have terminals that are connected to ground with voltage controlled, voltage s... | 02/19/2008 |
| 7282963 | Wide-band circuit coupled through a transmission line To provide a broadband circuit from which a desired circuit characteristic is stably obtained over a wide frequency band with a small number of circuit devices and which can be easily designed. In the case of the broadband circuit to which a circuit device is connec... | 10/16/2007 |
| 7259595 | Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit A frequency detection circuit and method of detecting the frequency of a clock signal, and a latency signal generation circuit for a semiconductor memory device that includes the frequency detection circuit. The frequency detection circuit includes a frequency detec... | 08/21/2007 |
| 7251300 | Method and apparatus for frequency tracking based on recovered data A method of frequency tracking based on recovered data, for use in an automatic frequency control subsystem at the receiver of a mobile station, is disclosed. The frequency tracking mechanism derives frequency error information from the recovered data to determine t... | 07/31/2007 |
| 7242223 | Clock frequency monitor A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given ... | 07/10/2007 |
| 7227919 | Data sampler for digital frequency/phase determination A digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an... | 06/05/2007 |
| 7224751 | Device and method for checking whether a signal with a predetermined frequency is being received A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The inventio... | 05/29/2007 |
| 7202751 | Optically pumped frequency standard with reduces AC stark shift An apparatus for generating a stabilized frequency signal is disclosed. The apparatus includes a quantum absorber having first, second, and third energy states. The quantum absorber is irradiated by a first radiation source that generates electromagnetic radiation h... | 04/10/2007 |
| 7171575 | Delay locked loop for and FPGA architecture A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is ... | 01/30/2007 |
| 7155372 | Methods and apparatuses for filtering pulses In one embodiment, a method that includes creating a filter structure using a parameter of a periodic pulse train, the filter structure having a plurality of time slots, each time slot being associated with a memory value; receiving a pulse at a time; incrementing t... | 12/26/2006 |
| 7095259 | Reducing metastable-induced errors from a frequency detector that is used in a phase-locked loop A technique for reducing the likelihood that a frequency detector will incorrectly assert control over a VCO because of metastable-induced errors involves qualifying frequency detector control signals by requiring multiple consecutive control signals that indicate t... | 08/22/2006 |
| 7027545 | Data sampler for digital frequency/phase determination The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a know... | 04/11/2006 |
| 7015725 | Delay-locked loop device capable of anti-false-locking A delay-locked loop device capable of anti-false-locking includes a voltage control delay circuit including a plurality of delay units in a series for generating a delayed phase according to a reference phase and a control voltage; a phase detector coupling to the v... | 03/21/2006 |
| 7009894 | Dynamically activated memory controller data termination A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memor... | 03/07/2006 |
| 6982606 | Method and device for dynamically calibrating frequency The method and the device thereof for dynamically calibrating a frequency is provided. The method includes steps of: (a) providing a first system frequency; (b) obtaining a first parameter of timer counting number; (c) providing a second system frequency; (d) obtain... | 01/03/2006 |
| 6961287 | Time error compensating apparatus and method in a terminal A time-error-compensating apparatus and method corrects errors in a real-time clock caused by temperature fluctuations or other external influences. The apparatus includes a frequency counting unit which counts a high-frequency clock signal and a low-frequency clock... | 11/01/2005 |
| 6949959 | Method for converting electric signals and a converter therefor The invention relates to signal conversion devices to be used for the receiving radio devices. The attained technical result is the detection and conversion of signals in an electrical two-terminal device, a data loss level being minimal. A converting element is sup... | 09/27/2005 |
| 6937069 | System and method for dead-band determination for rotational frequency detectors In one embodiment a system and method is arranged for bridging the dead-band when asynchronous signals are compared against each other. There is developed a pair of phase related signals from one of the signals, each phase related signal phase shifted from each othe... | 08/30/2005 |
| 6911873 | Detection circuit and method for an oscillator A method and circuit are disclosed for detecting the performance of an oscillator circuit. In particular, the circuit may detect a signal, such as the output of the oscillator circuit, failing to oscillate as desired. The second circuit may be capable of detecting w... | 06/28/2005 |
| 6681190 | Method and system of harmonic regulation A system and method of harmonic regulation includes a harmonic regulator configured to cancel or inject harmonics into a power conversion system. A resettable integrator is provided to determine at least one harmonic coefficient of the at least one error ... | 01/20/2004 |
| 6680631 | Setting the speed of clocked circuitry A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set ... | 01/20/2004 |
| 6591369 | System and method for communicating with an integrated circuit A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protoco... | 07/08/2003 |
| 6580297 | Frequency comparison circuit The objective of the invention is to provide technology to give high-speed DVD RF signal reading. Frequency comparison circuit 1 of the present invention has edge spacing detection circuit 3, maximum spacing detection circuit 4, and minimum spacing detect... | 06/17/2003 |
| 6553496 | Integration of security modules on an integrated circuit An integrated circuit includes secure logic that requires protection. Secure assurance logic protects the secure logic. The secure assurance logic includes a plurality of protection modules that monitor the occurrence of insecure conditions. Each protecti... | 04/22/2003 |
| 6525568 | Circuit for the demodulation of the logic signal transmitted by analog channels In digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits, the signals are received in analog form and have to be converted into logic levels. This is done in practice by comparing the level o... | 02/25/2003 |
| 6353368 | VCO circuit using negative feedback to reduce phase noise A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage convert... | 03/05/2002 |
| 6337682 | Flat panel display apparatus with automatic coarse control A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a phase detector for detecting the phase difference between the sampling... | 01/08/2002 |
| 6313669 | Buffer circuitry There is provided buffer circuitry that can include a data output circuit for connecting a first power supply to its output terminal when a data applied thereto is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW le... | 11/06/2001 |
| 6259279 | High frequency detection circuit and method The present invention is a high frequency detection circuit (10) which includes a high frequency filter (12) and a frequency comparator (14) which compares the output of the high frequency filter with the incoming clock signal to determine if the high fre... | 07/10/2001 |
| 6188257 | Power-on-reset logic with secure power down capability Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-... | 02/13/2001 |
| 6175882 | Network system for a first module port auto configuring same mode as a second module port A system and technique of auto-configuring a first module to be in the same mode as a second module includes testing the frequency of a clock signal received from the second module to determine its mode of operation. The first module then auto-configures ... | 01/16/2001 |