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| Number | Title | Issue Date |
| 7570098 | Active voltage-clamping gate driving circuit An active voltage-clamping gate driving circuit comprises a difference comparison circuit for receiving a reference voltage, a gate driving signal, and a preset voltage level, and outputting a voltage comparison signal; and a gate driving circuit for receiving an in... | 08/04/2009 |
| 7423471 | Backflow preventing circuit capable of preventing reverse current efficiently This patent specification describes a backflow prevention circuit which includes a first switch configured to conduct or to shut down a current path from an input terminal to an output terminal, a logic circuit configured to binarize an input voltage at the input te... | 09/09/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372291 | Circuits having precision voltage clamping levels and method A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver... | 05/13/2008 |
| 7348809 | Input buffer In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a w... | 03/25/2008 |
| 7339429 | Adjusting methods of arithmetic multiplying circuit, drive circuit, and phase margin An arithmetic amplifying circuit for driving a capacitive load is provided including a voltage follower circuit converting an input signal to impedance, and a resistance circuit which is serially connected between the voltage follower circuit and an output of the ar... | 03/04/2008 |
| 7280419 | Latency counter having frequency detector and latency counting method thereof The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one delay amount to the input clock to generate a delayed input clock; a f... | 10/09/2007 |
| 7248092 | Clamp circuit device In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap refere... | 07/24/2007 |
| 7236002 | Digital CMOS-input with N-channel extended drain transistor for high-voltage protection A circuit and a method are given, to realize an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a high-voltage range exceeding said standard CMOS low-voltage operating range s... | 06/26/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7218496 | Overcurrent protection circuit The voltage generator circuit includes a regulator, a first sensor circuit, and a second sensor circuit. The first sensor circuit includes a first transistor, a first resistor, and an error amplifier. When V1>Vth, the error amplifier senses an overcurrent con... | 05/15/2007 |
| 7205818 | Current loop drive module with dynamic compliance voltage A current loop drive module includes a drive circuit and a compliance voltage controller. The drive circuit is configured to receive a compliance voltage and operable to generate a current loop signal based on the compliance voltage for receipt by an associated load... | 04/17/2007 |
| 7197381 | Navigational system and method utilizing sources of pulsed celestial radiation A system and method for navigation utilizing sources of pulsed celestial radiation are provided. A spacecraft, satellite, or other vehicle (12) has a pulse sensor (22) mounted thereto for detecting signal pulses (14) generated by a plurality of ... | 03/27/2007 |
| 7159067 | Information processing apparatus using index and TAG addresses for cache In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache conten... | 01/02/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7142033 | Differential clocking scheme in an integrated circuit having digital multiplexers A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differentia... | 11/28/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7126406 | Programmable logic device having an embedded differential clock tree A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements... | 10/24/2006 |
| 7106129 | Semiconductor device less susceptible to variation in threshold voltage A threshold compensating circuit generates a bias potential VBIAS, that is, a threshold voltage of a MOS transistor offset by a given value. A gate-source voltage having compensation for variation in threshold voltage is thus applied to a transistor. By using a diff... | 09/12/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7084692 | Control of a thyristor of a rectifying bridge A method and a circuit for controlling at least one thyristor constitutive of a rectifying bridge with a filtered output, including closing the thyristor when the voltage thereacross becomes greater than zero, and making the gate current of the thyristor disappear w... | 08/01/2006 |
| 7078942 | Driving apparatus for generating a driving current using PWM A current driving apparatus includes a first square wave generator (100), a second square wave generator (200), an FET (Field Effect Transistor) (3), and a power supply (9). The first square wave generator has an output connected to the s... | 07/18/2006 |
| 7071756 | Clock multiplexing system A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second diffe... | 07/04/2006 |
| 7050342 | Testmode to increase acceleration in burn-in A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each memory cell in each memory array block is accessed to ensure proper functionality. By providing logic ga... | 05/23/2006 |
| 7042914 | Calibrated data communication system and method A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second devic... | 05/09/2006 |
| 7042280 | Over-current protection circuit A regulator system includes a power device and a sense device. During a normal operating mode, the power device is arranged to deliver current to a load, while the sense device is arranged to monitor the load current. An over-current mode is activated when the sense... | 05/09/2006 |
| 7027307 | Clock routing in multiple channel modules and bus systems An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory mo... | 04/11/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 7015745 | Apparatus and method for sensing current in a power transistor A circuit for regulating a sensed current in a power transistor is provided. The circuit is configured to sense if the drain current of the power transistor has reached a limit current Ilimit. A sense transistor is arranged in an m:1 current mirror relati... | 03/21/2006 |
| 7013118 | High speed operational amplifier design A radio receiver portion of a transceiver includes a differential amplifier that is used to provide a fast response. A pair of input MOSFETs of the differential amplifier stage are coupled to an active load. A voltage follower circuit is coupled to each output stage... | 03/14/2006 |
| 7005913 | I/O buffer with wide range voltage translator In accordance with an aspect of an input/output device for providing fast translation between differential signals from a core of an integrated circuit and higher voltage signals that are external to the core, an I/O buffer includes low voltage devices for receiving... | 02/28/2006 |
| 7002401 | Voltage buffer for capacitive loads A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is conn... | 02/21/2006 |
| 6959016 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the... | 10/25/2005 |
| 6956412 | High-voltage input tolerant receiver A high-voltage input tolerant receiver capable of achieving power savings with less distortion of analog signals is disclosed. When an external signal φC input from a PAD 2 is less than 3.6V, a p-channel MOS transistor P10 is turned off. As a result, ... | 10/18/2005 |
| 6954097 | Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ... | 10/11/2005 |
| 6952462 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 10/04/2005 |
| 6949963 | Line driver with current source output and high immunity to RF signals Line driver for a LIN-bus. The line driver has a current source output transistor (T1) for pulling down the LIN-bus wire (LB) to ground (GND). The LIN-bus wire (LB) is connected to a positive supply voltage (VBAT) through a pull-up resistor (R1). The o... | 09/27/2005 |
| 6946910 | Configurable feedback path in an amplitude control system A configurable feedback path is included in an amplitude control system having a signal source and an amplitude controller, and provides accurate tracking between a signal provided at a test port and a reference signal, whether or not the configurable feedback path ... | 09/20/2005 |
| 6937078 | Circuit configuration for regenerating clock signals A circuit configuration regenerates clock signals. The circuit configuration includes an input differential amplifier, first and second inverters, and an offset compensation circuit. The input differential amplifier generates first and second amplified signals in re... | 08/30/2005 |
| 6933753 | Sensor signal output circuit A sensor signal output circuit includes a first differential amplifier, a first load resistor, a first transistor, a second transistor and a limiter section. The limiter section includes at least a second differential amplifier, which includes an input end coupled t... | 08/23/2005 |
