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| Number | Title | Issue Date |
| 7982517 | Delay line A delay line includes a delay amount adjusting unit configured to adjust a delay amount of an input signal in response to a first delay control code, and a delay unit configured to determine a number of first delay blocks having a delay amount with a first variation... | 07/19/2011 |
| 7714630 | Method and apparatus to limit circuit delay dependence on voltage The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an inpu... | 05/11/2010 |
| 7554375 | Delay line circuit Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals. ... | 06/30/2009 |
| 7417482 | Adaptive voltage scaling for an electronics device Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit compo... | 08/26/2008 |
| 7382170 | Programmable delay circuit having reduced insertion delay A programmable delay circuit includes a plurality of delay blocks, a plurality of corresponding tri-state drivers and at least one decoder. The delay blocks are connected together so as to form a series chain. Each of the tri-state drivers includes an input connecte... | 06/03/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7366048 | Bulk bias voltage level detector in semiconductor memory device There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a sem... | 04/29/2008 |
| 7362127 | Driver circuit A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power ba... | 04/22/2008 |
| 7355461 | Waveform generating circuit and spread spectrum clock generator A waveform generating circuit is provided which generates a modified triangular wave signal suitable for being input to a frequency modulation circuit such as a voltage-controlled oscillator (VCO). The waveform generating circuit includes a triangular generator, an ... | 04/08/2008 |
| 7355435 | On-chip detection of power supply vulnerabilities On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outs... | 04/08/2008 |
| 7355458 | Output driver circuit and a method of transmitting an electrical signal via an output driver circuit In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal whic... | 04/08/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7348811 | Equalizing transceiver with reduced parasitic capacitance A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a cor... | 03/25/2008 |
| 7339408 | Generating multi-phase clock signals using hierarchical delays Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD inclu... | 03/04/2008 |
| 7331006 | Multiple sweep point testing of circuit devices An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part... | 02/12/2008 |
| 7327184 | Low-power multi-level pulse amplitude modulation driver and semiconductor device having the driver A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input tra... | 02/05/2008 |
| 7327179 | Pulse generator, optical disk writer and tuner A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator and a selecting arrangement for selecting how many of a first group of delay elements are connected in series for delaying ... | 02/05/2008 |
| 7327331 | Apparatus for generating ramp reset waveform for display panel and design method therefor A ramp reset waveform generating apparatus in a display panel driving apparatus for a display panel includes a current source which is connected to a first electrode sustain circuit of the display panel through a first terminal of the current source, and generates a... | 02/05/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7321254 | On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillator... | 01/22/2008 |
| 7317341 | Duty correction device A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a pulse width of an input clock and output the adjusted clock as an outpu... | 01/08/2008 |
| 7315469 | Control of set/reset pulse in response to peripheral temperature in PRAM device A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a p... | 01/01/2008 |
| 7304521 | Delay circuit for synchronizing arrival of a clock signal at different circuit board points A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize ... | 12/04/2007 |
| 7304516 | Method and apparatus for digital phase generation for high frequency clock applications An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal.... | 12/04/2007 |
| 7304520 | Delay circuit and semiconductor device including same A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays... | 12/04/2007 |
| 7302461 | Analog delay elements Systems and methods provide analog delay elements, which may be utilized in isolation or in a cascade. For example, a delay element may include a broadband amplifier and a passive, programmable filter, which may provide a desired magnitude and group delay response o... | 11/27/2007 |
| 7302055 | Discharging envelope detector A receiver to detect pulses on a home phone wiring network using envelope detection. The receiver comprises an integrating capacitor charged by a first current source responsive to a differential signal propagated on the wiring network, and discharged by a FET in co... | 11/27/2007 |
| 7286000 | Semiconductor device A semiconductor device can accurately control the timings of various signals used in the semiconductor device using a simple configuration. The semiconductor device includes first fuse units which output first fuse signals, respectively, a first decoder which receiv... | 10/23/2007 |
| 7282977 | Duty cycle correction device Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first si... | 10/16/2007 |
| 7282975 | Apparatus and method to control self-timed and synchronous systems An apparatus includes a substrate, a target timing circuit, a leakage timing circuit, and a control unit. The target timing circuit and the leakage timing circuits are formed on the substrate. The target timing circuit has a target timing circuit frequency related t... | 10/16/2007 |
| 7279938 | Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) accord... | 10/09/2007 |
| 7276940 | Buffer/voltage-mirror arrangements for sensitive node voltage connections The present invention is directed to buffer/voltage mirror arrangement for sensitive node voltage connections. ... | 10/02/2007 |
| 7271638 | Delay circuit and delay synchronization loop device A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay uni... | 09/18/2007 |
| 7271637 | Circuit and method of controlling a delay of a semiconductor device A delay control circuit capable of controlling a delay time is disclosed. The delay control circuit includes a delay detecting circuit, a first pulse generator, a counter control circuit and a counter. The delay detecting circuit delays an input signal by a first ti... | 09/18/2007 |
| 7254208 | Delay line based multiple frequency generator circuits for CDMA processing A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay lin... | 08/07/2007 |
| 7251739 | System and method for sequencing multiple write state machines In some embodiments, systems and methods for sequencing multiple write state machines may comprise a pulse generator, a delay circuit, and a stacked memory array, wherein each memory array in the stacked memory array have an individual write state machine. In an exe... | 07/31/2007 |
| 7249290 | Deskew circuit and disk array control device using the deskew circuit, and deskew method A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent befor... | 07/24/2007 |
| 7245540 | Controller for delay locked loop circuits A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external... | 07/17/2007 |
| 7239575 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 07/03/2007 |
