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| Number | Title | Issue Date |
| 8134396 | Dynamic element matching for delay lines This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching. ... | 03/13/2012 |
| 7432753 | Delay circuit and semiconductor device A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for ... | 10/07/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7352826 | Analog delay circuit An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor a... | 04/01/2008 |
| 7348821 | Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable... | 03/25/2008 |
| 7350093 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 03/25/2008 |
| 7343507 | Input circuit and method for the operation thereof An input circuit (1′) provided with a time delay element (40), which circuit is capable of being tested by a controlled high level or low level connection, and a method for the operation thereof. The delay time of the time-delay element can be modifi... | 03/11/2008 |
| 7315593 | Hyperfine oversampler method and apparatus A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold windows for adjacent samplers. Subsequent processing of the sample stream... | 01/01/2008 |
| 7313051 | Output control signal generating circuit An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the... | 12/25/2007 |
| 7292086 | Delay circuit and semiconductor device A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for se... | 11/06/2007 |
| 7279944 | Clock signal generator with self-calibrating mode A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for... | 10/09/2007 |
| 7278045 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 10/02/2007 |
| 7276946 | Measure-controlled delay circuits with reduced phase error Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic pr... | 10/02/2007 |
| 7275172 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 09/25/2007 |
| 7274605 | Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adj... | 09/25/2007 |
| 7272742 | Method and apparatus for improving output skew for synchronous integrated circuits A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffer... | 09/18/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7256636 | Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexe... | 08/14/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7239189 | Clock generating circuit A clock generating circuit includes a first delay circuit array, which has a plurality of delay circuits, for measuring delay of an input signal, and a second delay circuit array for delay-replay having a plurality of delay circuits and being arranged in a direction... | 07/03/2007 |
| 7236009 | Operational time extension Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circu... | 06/26/2007 |
| 7233170 | Programmable driver delay Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a ... | 06/19/2007 |
| 7233185 | Vernier circuit for fine control of sample time A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temper... | 06/19/2007 |
| 7231620 | Apparatus, generator, and method for clock tree synthesis A clock tree synthesis (CTS) apparatus, generator, and method for synthesizing a clock tree includes a plurality of clock signal generators that output different clock signals generated from a reference clock signal. The clock signal generators includes an additiona... | 06/12/2007 |
| 7205803 | High speed fully scaleable, programmable and linear digital delay circuit The digitally programmable delay circuit to correct timing skew between data and clock is developed. The digitally programmable delay circuit may be built by cascading delay cells. The delay circuit uses delay cells comprising simple digital elements such as inverte... | 04/17/2007 |
| 7180330 | Output circuit An output circuit includes: a power supply unit; an output MIS transistor connected to the power supply unit; a reference MIS transistor that is connected to the power supply unit and is invariably in ON state; a current supply unit for generating a reference voltag... | 02/20/2007 |
| 7167523 | Spacial derivative bus encoder and decoder A method and apparatus for providing efficient and accurate electronic data transmission of information on a data bus in the presence of noise. Data signals are received on a plurality of input lines by a spacial derivative encoder. The spacial derivative encoder en... | 01/23/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7154312 | Apparatus for generating internal clock signal An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for ... | 12/26/2006 |
| 7135903 | Phase jumping locked loop circuit A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair ... | 11/14/2006 |
| 7126401 | Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be d... | 10/24/2006 |
| 7119593 | Delayed signal generation circuits and methods Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked ... | 10/10/2006 |
| 7119592 | Delay locked loop circuit with time delay quantifier and control A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a delay controller controls a correction delay quantity applied to a s... | 10/10/2006 |
| 7116589 | Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adj... | 10/03/2006 |
| 7106822 | Bidirectional synchronous interface with single time base A bidirectional synchronous interface for the reception of a first flow of digital data with a first coding from a communication channel, and for the transmission on the communication channel of a second flow of digital data with the first coding in synchrony with a... | 09/12/2006 |
| 7100066 | Clock distribution device and method in compact PCI based multi-processing system Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location... | 08/29/2006 |
| 7091764 | Duty distortion detector A duty distortion detector comprises a first synchronous mirror delay configured to mirror a first signal with respect to a clock signal to provide a second signal, and a second synchronous mirror delay configured to mirror the second signal with respect to an inver... | 08/15/2006 |
| 7088163 | Circuit for multiplexing a tapped differential delay line to a single output A method and circuit to adjust timing between received differential data and clock signals to compensate for differences between transmission paths of data and clock signals. According to one embodiment, a timing adjustment circuit includes a decoder, a differential... | 08/08/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
