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Vehicular Impact Signaling Device
An apparatus for the deployment of a visible plume to alert other motorists that a proximate motor vehicle has been involved in a collision.
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| Number | Title | Issue Date |
| 6535043 | Clock signal selection system, method of generating a clock signal and programmable clock manager including same For use with a programmable clock manager (PCM), a selection system and method of generating a clock signal. In one embodiment, the selection system includes a phase selector, having multiple taps, configured to generate multiple phase shifted signals fro... | 03/18/2003 |
| 6525583 | Circuit configuration for enhancing performance characteristics of fabricated devices A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transi... | 02/25/2003 |
| 6515529 | Semiconductor buffer circuit with a transition delay circuit The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay ci... | 02/04/2003 |
| 6504413 | Buffer improvement The present invention is directed to a buffer improvement for higher speed operation. A buffer may include at least two buffer stages, which may include a first buffer stage and a second buffer stage. A voltage conversion circuit is disposed between the f... | 01/07/2003 |
| 6493653 | Tapped delay line high speed register A clockless time-of-flight interval timer includes a tapped delay line register comprising N buffers that each contribute a substantially identical incremental time delay. A latched version of a START pulse associated with an output of transmitted energy ... | 12/10/2002 |
| 6492851 | Digital phase control circuit The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers (G1-G10) having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled... | 12/10/2002 |
| 6462597 | Trip-point adjustment and delay chain circuits Circuit techniques provide different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. Di... | 10/08/2002 |
| 6437617 | Method of controlling a clock signal and circuit for controlling a clock signal A method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T1-T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the exter... | 08/20/2002 |
| 6434061 | Circuit configuration for enhancing performance characteristics of fabricated devices A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transi... | 08/13/2002 |
| 6430725 | System and method for aligning output signals in massively parallel testers and other electronic devices Signal alignment circuitry aligns (i e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The dela... | 08/06/2002 |
| 6414557 | High noise rejection voltage-controlled ring oscillator architecture A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differenti... | 07/02/2002 |
| 6407607 | In and out of phase signal generating circuit In the present invention a signal generator is described for use in measuring the effects of wire to wire coupling in integrated circuits. A signal is connected to a wire that is surrounded by reference wires. A set of latches are used to set up and initi... | 06/18/2002 |
| 6400187 | Precision, low-power transimpedance circuit with differential current sense inputs and single ended voltage output A transimpedance circuit adapted for use in a subscriber line interface circuit includes sense resistors installed in closed loop, negative feedback paths of respective sense amplifiers. Voltage drops across the sense resistors are applied to first and se... | 06/04/2002 |
| 6400202 | Programmable delay element and synchronous DRAM using the same A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is co... | 06/04/2002 |
| 6396321 | Semiconductor integrated circuit equipped with function for controlling the quantity of processing per unit time length by detecting internally arising delay A semiconductor integrated circuit 10 comprises an internal logic circuit 16, a delay detecting circuit 11 which monitors changes in delay length within the semiconductor integrated circuit 10, and a central control circuit 14 which controls the quantity ... | 05/28/2002 |
| 6380784 | Circuit for generating sense amplifier control signal for semiconductor memory A circuit is provided that generates a sense amplifier control signal for a semiconductor memory in which signal paths for a normal operation and a refresh operation are separately formed so that a pulse width of an overdriving interval in the refresh ope... | 04/30/2002 |
| 6373312 | Precision, high speed delay system for providing delayed clock edges with new delay values every clock period A precision delay system allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry. The sy... | 04/16/2002 |
| 6335650 | Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multip... | 01/01/2002 |
| 6310503 | Delay circuit having a constant delay time The present invention discloses a delay circuit having a constant delay time. The delay circuit comprises an electric wire for transmitting a driving signal from a driver; a capacitor connected between said electric wire and ground, and for delaying trans... | 10/30/2001 |
| 6288587 | CMOS pulse shrinking delay element with deep subnanosecond resolution A CMOS pulse shrinking delay element with deep subnanosecond resolution applicable to a Time-to-Digital Converter (TDC) can control its pulse shrinking or expanding capability be adjusting the dimension ratio between internal adjacent elements. This elimi... | 09/11/2001 |
| 6278309 | Method of controlling a clock signal and circuit for controlling a clock signal A method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T1-T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the exter... | 08/21/2001 |
| 6278310 | Semiconductor buffer circuit with a transition delay circuit The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay ci... | 08/21/2001 |
| 6275077 | Method and apparatus for programmable adjustment of bus driver propagation times A bus driver introduces a propagation delay of programmable duration prior to transmission of data over a bus. The bus driver has an input stage for acquiring data for transmission over a bus and an output stage having a driver circuit for transmitting da... | 08/14/2001 |
| 6252445 | Method and apparatus for extending a resolution of a clock A method and apparatus for extending a resolution of a clock in which the resolution is limited by a period of an oscillator in the clock. The present method and apparatus employs delays which are adapted to the period of the clock and which enable the de... | 06/26/2001 |
| 6249166 | Pipelined programmable digital pulse delay A pipelined programmable digital pulse delay system (10) that is capable of processing multiple input pulses simultaneously, each with a unique programmed delay value, includes a plurality of pulse delay units (12, 14, 16), a plurality of buffer registers... | 06/19/2001 |
| 6232813 | Phase locked loop integrated circuits having fuse-enabled and fuse-disabled delay devices therein Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth... | 05/15/2001 |
| 6222396 | Electronic system having a multistage low noise output buffer system In one embodiment, a multistage output buffer supplies current to a load by successively turning ON output buffer circuits which transition from an OFF state to approximately a saturated state during approximately mutually exclusive periods of time. Thus,... | 04/24/2001 |
| 6222393 | Apparatus and method for generating a pulse signal A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the fir... | 04/24/2001 |
| 6215368 | Voltage controlled oscillating device Voltage controlling/oscillating device comprises a terminal for setting the delay rate in the delay unit and the delay interpolator. Clock signal whose phase is inverted by the inverting gate is inputted into a first input terminal of the delay interpolat... | 04/10/2001 |
| 6208182 | Phase-locked loop circuit The present invention relates to a phase-locked loop circuit including: a programmable ring oscillator generating drive signals, an assembly of latches receiving an input signal of the circuit, the latches being driven by the drive signals and generating ... | 03/27/2001 |
| 6201414 | Pulse width modulation circuit A pulse width modulation circuit utilizes a clock divider to generate a plurality of clocks to be used by a plurality of delay blocks. Each delay block has plurality of delay elements each of which receives one the plurality of clocks. Each delay block re... | 03/13/2001 |
| 6194937 | Synchronous delay circuit system A synchronous delay circuit system comprises an input buffer having a first delay time and receiving an external clock, a clock driver having a second delay time and for an internal clock, a dummy delay circuit having a delay time equal to a sum of the fi... | 02/27/2001 |
| 6188261 | Programmable delay generator and application circuits having said delay generator A programmable delay generator comprises a first ramp wave generator and a second ramp wave generator, each having the same structure as each other, each of them operating with external common clock pulses, and each of them providing potential gradient an... | 02/13/2001 |
| 6184753 | Clock delay circuitry producing clock delays less than the shortest delay element A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce... | 02/06/2001 |
| 6177846 | Ring oscillator type voltage controlled oscillator A voltage controlled oscillator includes plural cascade-connected unit circuits supplied with selection signals corresponding to an oscillation frequency. Each unit circuit includes a voltage controlled delay circuit, selection circuit and adder circuit. ... | 01/23/2001 |
| 6177823 | Pincer movement delay circuit for producing output signal different in repetition period from input signal A delay circuit has a first delay line propagating an input pulse from stage to stage in one direction, a second delay line propagating the previous input pulse from stage to stage in the opposite direction and a comparator operative compare output potent... | 01/23/2001 |
| 6169435 | Semiconductor integrated circuit device with built-in timing regulator for output signals A semiconductor integrated circuit device is expected to output a multi-bit output signal at an extremely narrow timing in response to a system clock, wherein the semiconductor integrated circuit device includes synchronous latch circuits, a first phase-l... | 01/02/2001 |
| 6163195 | Temperature compensated delay chain A delay circuit is provided for delaying signals. The delay circuit includes: at least one inverter having a time delay; at least one current source coupled to the at least one inverter, the at least one current source providing charging current to the at... | 12/19/2000 |
| 6158030 | System and method for aligning output signals in massively parallel testers and other electronic devices Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The dela... | 12/05/2000 |
| 6154078 | Semiconductor buffer circuit with a transition delay circuit The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay ci... | 11/28/2000 |
