Class 327/251 - Having multiple outputs

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein more than one output is produced.
No. of patents: 36
Last issue date: 01/22/2008

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Number	Title	Issue Date
7321249	Oscillator, frequency multiplier, and test apparatus There is provided an oscillator for generating an oscillating signal having desired frequency, having a reference oscillating section for generating a reference signal having predetermined frequency, a plurality of first variable delay circuits, connected in cascade...	01/22/2008
7253673	Multi-phase clock generator and generating method for network controller The present invention discloses a multi-phase clock generator of a network controller for generating a set of multi-phase clocks, and a method thereof. The multi-phase clock generator includes a first gating element and a second gating element. The first gating elem...	08/07/2007
7233185	Vernier circuit for fine control of sample time A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temper...	06/19/2007
7132857	High speed receiver with wide input voltage range A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is cou...	11/07/2006
7088156	Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ...	08/08/2006
7071750	Method for multiple-phase splitting by phase interpolation and circuit the same The invention relates to a method and related circuitry for multiple phase-splitting. The method includes: while generating M output clocks with a same frequency f1 and different phases, generating N reference clocks with a same frequency (M/N)*f1 and ...	07/04/2006
7002390	Delay matching for clock distribution in a logic circuit Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an ori...	02/21/2006
6954097	Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ...	10/11/2005
6940331	Delayed tap signal generating circuit for controlling delay by interpolating two input clocks A circuit and method of generating delayed tap signals can adjust a delay difference by interpolating two input clock signals as indicated by an offset information signal. In the circuit, first and second tap signals are generated by interpolating first and second c...	09/06/2005
6911856	Delay matching for clock distribution in a logic circuit Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an ori...	06/28/2005
6847238	Output circuit and method for reducing simultaneous switching output skew An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a de...	01/25/2005
6768356	Apparatus for and method of implementing time-interleaved architecture In accordance with a preferred embodiment, a time-interleaved (or multi-phase) architecture is provided having individual control of a plurality of output signals or phases. The time-interleaved architecture may be implemented using a first set of delay cells such a...	07/27/2004
6690223	System and method for shifting the phase of a clock signal An embodiment of this invention pertains to a digital circuit that shifts the phase of a clock signal. In this embodiment, multiple delay units, e.g., buffers, shift the clock signal multiple times and store a level of the clock signal within correspondin...	02/10/2004
6570425	Phase difference signal generator and multi-phase clock signal generator having phase interpolator In a phase difference signal generator, a first delay circuit has a delay time of nx where n ix 2, 3, . . . and x is a voluntary real number, the delay circuit receiving a first input clock signal having a phase of 0° to generate a first phase difference...	05/27/2003
6177822	Variable phase shifting circuit manufactured in simple integrated circuit A variable phase shifting circuit includes a resistance unit and a variable capacitance unit. The resistance unit includes at least one resistor element. The resistance unit input a first signal and a second signal and also output a third signal and a fou...	01/23/2001
6041089	Bit phase synchronizing method and bit phase synchronizing circuit (1) A bit phase adjusting circuit receives input data Din and passes it to a first group of delay gates which are connected in series to generate a set of data available for selection, the set including the input data Din and the input Din delayed by diff...	03/21/2000
5977809	Programmable non-overlap clock generator A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The prese...	11/02/1999
5939917	Voltage-controlled phase shifter The present invention relates to a voltage-controlled phase shifter including two differential stages, each including a biasing branch and output branches coupled with the output branches of the other stage; two first resistors coupling the output branche...	08/17/1999
5801566	System clock generating circuit for a semiconductor device According to the present invention, when a semiconductor device is tested, a signal for test can be set in the semiconductor device at a desired timing. A second delay circuit of the present invention has the same structure as a first delay circuit in a p...	09/01/1998
5737274	Sense amplifier design The present invention concerns a method and apparatus that generally prevents a glitch from occurring in an output of a sense amplifier during a transition from a strong zero to a weak zero. The present invention detects the voltage difference between a v...	04/07/1998
5565817	Ring oscillator having accelerated charging and discharging of capacitors In a ring oscillator, a delay unit includes an input stage having a first and a second input port and a first and a second differential output port. At least two delay units are coupled together so as to form the ring oscillator. The delay unit further in...	10/15/1996
5532633	Clock generating circuit generating a plurality of non-overlapping clock signals A first basic clock supplied from outside is delayed by a first delay circuit to generate a second basic clock which is fed to a frequency divider to generate a group of multi-phase clocks, each of which has a clock width equal to an integer number multip...	07/02/1996
5471162	High speed transient sampler A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates ...	11/28/1995
5184027	Clock signal supply system A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship...	02/02/1993
5159205	Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various...	10/27/1992
5087829	High speed clock distribution system This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in ...	02/11/1992
5066868	Apparatus for generating phase shifted clock signals Clock phase shifting circuitry includes a cascade connection of inverting amplifiers for generating a plurality of relatively delayed clock signals. Buffer amplifiers couple alternate ones of the inverting amplifiers to a clock phase selection circuit for...	11/19/1991
4994695	Synchronous delay line with quadrature clock phases A synchronous delay line with quadrature clock phases provides for an improved output from the taps of a delay line. The delay line is comprised of a phase generator, a plurality of voltage controlled delay stages arranged serially, wherein the last VCD s...	02/19/1991
4975605	Synchronous delay line with automatic reset An automatic reset scheme for a synchronized delay line detects the polarity of the tap signals from a predetermined number of delay stages. If the delay line powers up to lock onto one of the non-fundamental modes of operation, an inverted polarity is de...	12/04/1990
4849702	Test period generator for automatic test equipment A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connect...	07/18/1989
4700350	Multiple phase CRC generator A multiple phase CRC (cyclic redundancy check) generator having a clock phasing circuit having an input connected to the CRC clock source and a plurality of N phase clock outputs, and a plurality of N CRC circuits each having a data input, and a phase clo...	10/13/1987
4359689	Clock pulse driver A clock pulse driver has applied to it a system clock pulse signal, or system clock and produces a first set of individually enabled clock pulse signals, the leading edges of the pulses of which substantially coincide with the leading edges of the pulses ...	11/16/1982
4180778	Digital signal phase shifting system A digital signal phase shifting system which comprises a timing signal generator producing cyclic digitally coded timing signals; a first system output signal generator capable of decoding the timing signals and producing first system output signals in re...	12/25/1979
4167707	Symmetrical digital phase shifter A symmetrical phase shifter generates two signals shifted symmetrically from an inputted single signal, using digital delay lines....	09/11/1979
4021740	Sinewave clock driver with adjustable delay A sinewave clock distribution network and a clock driver for use in the network permit simplified distribution and synchronization in very high speed logic and digital transmission systems. The sinewave central clock is connected through a branching netwo...	05/03/1977
3987313	Arrangement for the generating of pulse trains for charge-coupled circuits An arrangement for generating pulse trains for charged-coupled circuits employs a plurality of series-connected master-slave JK flip-flop circuits in which a Q output of a flip-flop circuit is connected to a J input of the following flip-flop circuit and ...	10/19/1976

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Class 327/251 - Having multiple outputs