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| Number | Title | Issue Date |
| 7710178 | Delay apparatus for delay locked loop A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconduct... | 05/04/2010 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7284143 | System and method for reducing clock skew In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal a... | 10/16/2007 |
| 7278044 | Semiconductor memory device for reducing address access time An apparatus for controlling operations of a synchronous semiconductor memory device, wherein each operation is achieved by a plurality of internal instructions includes a reference clock block for receiving an external clock and outputting a plurality of delayed cl... | 10/02/2007 |
| 7257036 | Method and apparatus for storage device read phase auto-calibration The present invention provides a method and apparatus for performing read phase auto-calibration of a storage device. The method includes writing the data with at least one predetermined pattern into the storage device, reading the data according to a read phase of ... | 08/14/2007 |
| 7249290 | Deskew circuit and disk array control device using the deskew circuit, and deskew method A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent befor... | 07/24/2007 |
| 7239575 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 07/03/2007 |
| 7224639 | Multi-phase clock signal generator and method having inherently unlimited frequency capability A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay u... | 05/29/2007 |
| 7205811 | Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an as... | 04/17/2007 |
| 7187243 | Delay circuit A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements ... | 03/06/2007 |
| 7184936 | Timing variation measurement system and method The present invention is a system and method that facilitates measurement of timing variations (e.g., timing delays) in a semiconductor chip. The timing variations are measured and presented as digital values without extensive off chip measurement and analysis equip... | 02/27/2007 |
| 7180340 | Frequency multiplier capable of adjusting duty cycle of a clock and method used therein Provided is a frequency multiplier including a delay circuit, an XOR gate, and a control circuit and a method of operating such a frequency multiplier to adjust the duty cycle of a clock signal. During operation of the frequency multiplier the delay circuit receives... | 02/20/2007 |
| 7109768 | Closed-loop control of driver slew rate A device includes an output circuit to output an output signal. The device also includes a control loop circuit to measure the real slew of the output signal. The control loop circuit compares the real slew with a target slew adjusts the output circuit when the real... | 09/19/2006 |
| 7106655 | Multi-phase clock signal generator and method having inherently unlimited frequency capability A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay u... | 09/12/2006 |
| 7084689 | Method and apparatus for generating non-skewed complementary signals through interpolation A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at G... | 08/01/2006 |
| 7020792 | Method and apparatus for time domain equalization A method and apparatus is described that may be utilized to equalize modal velocity changes on a data bus. Modal velocity changes may be equalized by use of variable delays that may be used to equalize modal velocity changes. ... | 03/28/2006 |
| 7002390 | Delay matching for clock distribution in a logic circuit Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an ori... | 02/21/2006 |
| 6978403 | Deskew circuit and disk array control device using the deskew circuit, and deskew method A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent befor... | 12/20/2005 |
| 6911856 | Delay matching for clock distribution in a logic circuit Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an ori... | 06/28/2005 |
| 6166573 | High resolution delay line A high resolution delay line includes a coarse delay having a minimum period of delay and a fine delay having a total delay, wherein the total delay is equal to or greater than half the minimum period. Each delay can be implemented in analog or digital fo... | 12/26/2000 |
| 6049240 | Logical delaying/advancing circuit used An oscillating means having an oscillator outputs a reference clock, and a frequency-dividing means sequentially frequency-dividing the reference clock into a half frequency. A temperature correction data creating means detects a temperature, calculates l... | 04/11/2000 |
| 5986491 | Clock signal generator The clock signal generator can be used to generate a first and/or a second output clock signal from an input clock signal. The rising and/or falling edges of the input clock signal are shifted using delay stages. The clock signal generator has a delay sta... | 11/16/1999 |
| 5825226 | Delay equalization apparatus and method A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of th... | 10/20/1998 |
| 5808497 | Digital phase shifter The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2π is divided by 2π and mu... | 09/15/1998 |
| 5784272 | Control system for a process that exhibits periodic disturbances In a control system a characteristic quantity of a process (1) exhibits a periodic disturbance. A measuring system (2) generates a measuring signal (Vm) which represents the characteristic quantity. A control device controls the process in response to the... | 07/21/1998 |
| 5654659 | Scan circuit having a reduced clock signal delay A scan circuit includes a plurality of stages of cascaded pulse delay transfer circuits each including a single-phase-clock controlled inverter connected in cascade and configured to receive a given pulse signal from a preceding stage so as to transfer th... | 08/05/1997 |
| 5646564 | Phase-locked delay loop for clock correction A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship ... | 07/08/1997 |
| 5485128 | Oscillation circuit having a current-controlled phase shift circuit An oscillator circuit including a current-controlled phase shift circuit and a feedback circuit including a quartz resonator is capable of varying the oscillation frequency in accordance with control current signals. A phase shift circuit included in the ... | 01/16/1996 |
| 5471165 | Signal processing circuit and a method of delaying a binary periodic input signal A signal processing circuit delays a binary periodic input signal. Three series-connected delay devices produce output signals that are delayed in relation to the input signal. The delay of the delay devices can be controlled to a very high degree of accu... | 11/28/1995 |
| 5459402 | Delay time measuring circuit A delay time measuring circuit includes a delay circuit for changing the delay times of first and second clock signals output to measure the delay time of an evaluated circuit according to an externally supplied control voltage, and a voltage controlled o... | 10/17/1995 |
| 5440514 | Write control for a memory using a delay locked loop A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). ... | 08/08/1995 |
| 5223755 | Extended frequency range variable delay locked loop for clock synchronization A Delay Locked Loop For Clock Synchronization is disclosed that solves the problem of aligning a clock signal (VOUT) with a reference signal (REF) in the shortest time and without instability. The clock signal (VOUT) is passed throug... | 06/29/1993 |
| 5221863 | Phase-locked loop clock signal generator A variable delay circuit delays an input signal by an amount corresponding to a control signal. A signal delay amount of the variable delay circuit is detected by a delay amount detector circuit, and the detection signal is supplied to a charge pump circu... | 06/22/1993 |
| 5218314 | High resolution, multi-frequency digital phase-locked loop The present invention provides a phase-locked loop in which an internal oscillator is fed into a high resolution tapped delay line. One output of the tapped delay line is selected by selection logic to generate the output clock. The output clock is phase ... | 06/08/1993 |
| 5216302 | Reference delay generator and electronic device using the same A reference delay generator includes a delay unit having a plurality of delay elements which are cascaded and respectively have variable delay times. The delay unit receives a reference signal and generates a delayed signal which is a delayed version of t... | 06/01/1993 |
| 5204559 | Method and apparatus for controlling clock skew A circuit for controlling clock skew has a plurality of delay elements placed in each of the clock output paths in a clock distribution circuit. The delay elements may be selectively switched into or out of each clock output path in order to adjust the de... | 04/20/1993 |
| 5191295 | Phase shift vernier for automatic test systems A phase shift vernier for providing an output signal with continuously variable delay based on an input phase delay is disclosed. The apparatus comprises delay value means, a ring oscillator, a multiplexer, a DAC, and a signal combiner. The delay value me... | 03/02/1993 |
| 5173617 | Digital phase lock clock generator without local oscillator A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tappe... | 12/22/1992 |
| 5164677 | Method and apparatus for synchronizing signals A method and apparatus for synchronizing two signals having a phase relationship and originating from transmission lines having unknown and differing skew includes a variable delay element with adjustable delay responsive to an applied biasing voltage ins... | 11/17/1992 |
| 5150068 | Clock signal supply method and system The present invention provides a clock signal supply method and system. A reference signal and a synchronizing signal are generated, as well as a clock signal, at a clock signal generating source end. Both the reference signal and the synchronizing signal... | 09/22/1992 |
