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| Number | Title | Issue Date |
| 7433430 | Wireless communications device providing enhanced block equalization and related methods A wireless communications device may include a wireless receiver receiving signals having alternating known and unknown symbol portions over a channel, and a demodulator systolic array. The demodulator systolic array may include a channel estimation module generatin... | 10/07/2008 |
| 7433392 | Wireless communications device performing block equalization based upon prior, current and/or future autocorrelation matrix estimates and related methods A wireless communications device may include a wireless receiver for receiving signals comprising alternating known and unknown symbol portions, and a demodulator connected thereto. The demodulator may include a channel estimation module for generating respective ch... | 10/07/2008 |
| 7403054 | Sub-picosecond multiphase clock generator A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, whi... | 07/22/2008 |
| 7400211 | High speed passband phase modulation apparatus and method of the same A high speed passband phase modulation apparatus and method are provided. In the phase modulation apparatus, an RF phase shifter modulates a phase of a local signal that is generated in a VCO according to a digital input. The RF phase shifter is controlled by a phas... | 07/15/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7315599 | Skew correction circuit A skew correction circuit includes a first circuit and a second circuit. The first circuit generates at least one pulse train signal in response to a data bit signal and a first strobe signal. A duty cycle of the pulse train signal is indicative of a degree of skew ... | 01/01/2008 |
| 7268599 | Method and apparatus for buffer with programmable skew A method and apparatus for a buffer with programmable skew have been disclosed. Several output signals are generated. Based on one of the output signals several feedback signals are generated. The feedback signals are then received and compared. Based on the compari... | 09/11/2007 |
| 7263149 | Apparatus and method for generating a distributed clock signal The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a differen... | 08/28/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7123103 | Systems and method for automatic quadrature phase imbalance compensation using a delay locked loop An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to i... | 10/17/2006 |
| 7095801 | Phase adjustable polyphase filters A polyphase filter for wireless communication systems includes at least two phase splitting filters each having a variable resistance across their respective outputs. The variable resistance can take any suitable form, such as a MOS transistor biased in the linear (... | 08/22/2006 |
| 7088156 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 08/08/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7053687 | Binary hysteresis comparator circuits and methods Binary hysteresis comparator circuits, methods, and applications. A binary constant defines a window within which a binary input can change its value without triggering the comparator circuit output signal. An exemplary binary hysteresis comparator circuit includes ... | 05/30/2006 |
| 7038517 | Timing vernier using a delay locked loop A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first a... | 05/02/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 6970020 | Half-rate linear quardrature phase detector for clock recovery A half-rate linear phase detector is particularly well-suited to clock data recovery in a serial data interface. The phase detector uses a quadrature clock to process different portions of the incoming data with different phases of the clock. The resulting component... | 11/29/2005 |
| 6968436 | Memory controller that controls supply timing of read data A method for supplying a data signal read from a memory to an internal circuit of a semiconductor integrated circuit is described. First, supply timing information determining supply timing of the data signal provided to the internal circuit is generated using the d... | 11/22/2005 |
| 6959016 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the... | 10/25/2005 |
| 6954097 | Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ... | 10/11/2005 |
| 6952462 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 10/04/2005 |
| 6931086 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 08/16/2005 |
| 6897693 | Delay locked loop for improving high frequency characteristics and yield A delay locked loop (DLL) is provided that generates an internal clock signal in synchronization with an external clock signal. First through third amplifiers convert the swing width of the external clock signal to a small swing width and re-convert the external clo... | 05/24/2005 |
| 6853231 | Timing vernier using a delay locked loop A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the vernier being programmable to one of a plurality of timing steps within a delay range and the delay range being determined by a control signal applied t... | 02/08/2005 |
| 6520498 | Method and apparatus for detection of wrinkled documents in a sheet feeding device An apparatus and method for detecting wrinkling of sheets of material is provided. A change in an angle the sheet forms with a reference line can be detected. When the change in the angle exceeds a threshold value, wrinkling of the sheet can be detected. ... | 02/18/2003 |
| 6480049 | Multiphase clock generator The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential cir... | 11/12/2002 |
| 6407599 | Method and apparatus for determining a digital phase shift in a signal A method for determining a digital phase in a signal comprises sampling a reference signal for a low going edge. If the low going edge is not detected the reference signal is sampled again. If low going edge is detected (78) a counter is initialized (70).... | 06/18/2002 |
| 6400200 | Semiconductor integrated circuit which generates waveforms which are out of phase with each other A semiconductor integrated circuit comprises a phase control unit for shifting the phase of an input signal by two or more different fixed phases so as to generate two or more output signals out of phase. A phase detector detects phase differences among t... | 06/04/2002 |
| 6388485 | Delay-locked loop circuit having master-slave structure A delay-locked loop (DLL) circuit having a master-slave structure wherein the DLL circuit includes a master delay loop and a slave stage. The master delay loop delays an external clock signal by a predetermined delay time and generates a feedback signal w... | 05/14/2002 |
| 6380782 | Integrated circuit The integrated circuit has a clock input for an external clock signal and an output unit controlled by an internal clock signal in a normal mode of operation to output data to a data output. In addition, the integrated circuit has a control unit generatin... | 04/30/2002 |
| 6351166 | Semiconductor device with stable and appropriate data output timing A semiconductor device includes a timing-stabilization circuit which adjusts a phase of the synchronization clock signal. The semiconductor device further includes a control circuit which suspends the adjustment of the phase of the synchronization clock b... | 02/26/2002 |
| 6333653 | System and method for phase alignment of a plurality of clock pulses when starting, stopping and pulsing clocks The present invention is embodied in a clock controller for generating and controlling the phase alignment of a plurality of ratioed sub-clocks. A master clock is preferably input to a clock splitter to provide a plurality of slave clocks. Phase holds, ge... | 12/25/2001 |
| 6313680 | Phase splitter This invention provides a phase splitter device that generates in-phase and quadrature outputs that have a phase difference of substantially a phase set value (e.g., 90°) and an amplitude difference of substantially an amplitude set value (e.g., zero). A... | 11/06/2001 |
| 6310502 | Broadband phase shifting circuit having two phase shifter branches connected in parallel A broadband phase-shifting circuit, in particular for an IQ modulator, has two phase-shifting branches connected in parallel, to the input of which is supplied the input signal of which the phase is to be shifted, and which supply at their outputs output ... | 10/30/2001 |
| 6278309 | Method of controlling a clock signal and circuit for controlling a clock signal A method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T1-T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the exter... | 08/21/2001 |
| 6271696 | Phase adjustment circuit A phase adjustment circuit of the present invention includes a plurality of input terminals which input a plurality of clock signals, respectively, and a plurality of first elements which input the clock signals, respectively, and adjust the clock signals... | 08/07/2001 |
| 6208183 | Gated delay-locked loop for clock generation applications A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and s... | 03/27/2001 |
