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| Number | Title | Issue Date |
| 7969219 | Wide range delay cell A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) prov... | 06/28/2011 |
| 7872515 | Phase interpolation device and slew rate control device thereof A phase interpolation device and a slew rate control device thereof. The slew rate control device comprises a slew rate control circuit, source followers and a comparator. The slew rate control circuit receives clock signals and a control signal, and adjusts slew ra... | 01/18/2011 |
| 7825712 | Multi-phase clock signal generating circuit having improved phase difference and a controlling method thereof A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently con... | 11/02/2010 |
| 7795940 | Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device in... | 09/14/2010 |
| 7750707 | High-resolution low-interconnect phase rotator High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and... | 07/06/2010 |
| 7619456 | Wide frequency multi-phase signal generator with variable duty ratio and method thereof A multi-phase signal generator may include a duty control buffer configured to receive a first differential input signal and a second differential input signal, and generate a first differential output signal and a second differential output signal having variable d... | 11/17/2009 |
| 7579891 | Method and circuit arrangement for generating a periodic electric signal with controllable phase The invention relates to the generation of an electric output signal with a specified frequency and a phase (P) dependent upon a control signal (x) by means of weighted superposition of several input signals (s1, s2, s1*, s2*), which have... | 08/25/2009 |
| 7545193 | Voltage-controlled delay circuit using second-order phase interpolation Phase interpolation techniques for voltage-controlled delay line (VCDL) implementation are provided. The techniques of the invention may employ a second-order phase interpolation topology to improve tuning range performance of the VCDL over process and temperature v... | 06/09/2009 |
| 7420404 | Phase adjuster circuit and phase adjusting method A phase adjustor circuit and a phase adjusting method are capable of preventing a phase shift amount from fluctuating even if a frequency of a transmission carrier wave of a sensor signal fluctuates. A chopping wave converter circuit converts a pulse string signal i... | 09/02/2008 |
| 7362837 | Method and apparatus for clock deskew A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to ... | 04/22/2008 |
| 7362156 | Reliable phase adjustment circuit A phase adjustment circuit generates multiple clock signals by, for example, successively delaying a first clock signal. One of the generated clock signals is selected and output. A phase difference detector determines whether the phase of the selected clock signal ... | 04/22/2008 |
| 7324043 | Phase shifters deposited en masse for an electronically scanned antenna A system and method for an electronically scanned antenna is provided in which phase shifters are deposited en masse along with other electronically scanned antenna components on a wafer scale substrate using a thin film process. Alternative wafer scale sizes may be... | 01/29/2008 |
| 7304520 | Delay circuit and semiconductor device including same A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays... | 12/04/2007 |
| 7301383 | Circuit for controlling phase with improved linearity of phase change A circuit for controlling phase includes a first node providing a current responsive to a first clock signal, a first plurality of switch circuits coupled to the first node, a first plurality of current supply sources coupled to the first plurality of switch circuit... | 11/27/2007 |
| 7301410 | Hybrid current-starved phase-interpolation circuit for voltage-controlled devices A hybrid circuit includes a current-starved voltage-controlled circuit configured to adjust a first type of signal difference, and a phase-interpolated voltage controlled circuit configured to adjust a second type of signal difference. The current-starved circuit an... | 11/27/2007 |
| 7299006 | Adaptive radio transceiver An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged ... | 11/20/2007 |
| 7298194 | Interpolation A steering current generator for a phase interpolator has a multiplicity of fine phase adjustment current sources, each of which is switchable to direct its current to one or other of two summing nodes. The current of each of those two summing nodes is supplemented ... | 11/20/2007 |
| 7282979 | Phase shifting device A phase shifting device includes a signal source; a variable phase shifter; first and second doubling circuits; and a 90-degree phase comparator. An output from the signal source is connected to an input of the variable phase shifter and to an input of the second do... | 10/16/2007 |
| 7274276 | Amplifier circuit, gyrator circuit, filter device and method for amplifying a signal An amplifier circuit comprising a transconductor device connected to a phase shifter section. The phase shifter section has an adjustable phase shift and an impedance at least partially dependent of the frequency of an input signal. In use, the adjustable phase shif... | 09/25/2007 |
| 7265604 | High-frequency switch circuit arrangement A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltag... | 09/04/2007 |
| 7259606 | Data sampling clock edge placement training for high speed GPU-memory interface Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved data recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training ... | 08/21/2007 |
| 7246022 | Initiation of differential link retraining upon temperature excursion A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link. ... | 07/17/2007 |
| 7239218 | Phase shifter having switchable high pass filter and low pass filter paths and impedance adjustment circuits A phase shifter with a low insertion loss in which impedance mismatch at a point in rear of a high-pass filter or a low-pass filter in the signal flow direction is reduced and difference in insertion loss or phase shifting error across a high-pass filter- low-pass f... | 07/03/2007 |
| 7187243 | Delay circuit A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements ... | 03/06/2007 |
| 7183828 | Shift clock generator, timing generator and test apparatus There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion... | 02/27/2007 |
| 7181141 | Method and system for collecting network topology in an optical communications network An exemplary embodiment of the invention is a network element in an optical communications network. The network element includes a data collection application program interface (API) for receiving a request from a client for network topology information along with a... | 02/20/2007 |
| 7180352 | Clock recovery using clock phase interpolator A clock recovery circuit includes a delay locked loop, and a clock phase interpolator circuit. The delay locked loop provides multiple phases of an input clock signal to the interpolator circuit, which interpolates between two of the clock phases to provide a clock ... | 02/20/2007 |
| 7173466 | Timing signal generating circuit having simple configuration with low supply voltage and generating timing signals with high accuracy A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circui... | 02/06/2007 |
| 7167034 | Arrangement for correcting the phase of a data sampling clock signal during a period of sampling data in a received signal In a clock phase corrector appropriately correcting the phase of a data sampling clock signal, a series of shift registers responds to respective sampling clock signals to store received data sequentially. The stored data are duplicated by a comparator register in r... | 01/23/2007 |
| 7157949 | Delay locked loop capable of preventing false lock and method thereof A DLL capable of preventing false lock includes a false-lock detector, a delay line coupled for using at least one delay lag of the delay line to delay an incoming clock signal and produce at least one delay clock, and a charge pump coupled to the false-lock detecto... | 01/02/2007 |
| 7126442 | Phase shifter A phase shifter comprises: a phase shift unit including a reactance unit having a first variable capacitance device, and a susceptance unit having a second variable capacitance device, T-connected to the reactance unit; and a control unit for outputting a control si... | 10/24/2006 |
| 7102404 | Interpolator circuit An improved interpolator includes a replica delay line and an interpolated delay edge generator. The replica delay line provides two replica delay edges to the interpolated delay edge generator. The interpolated delay edge generator selectively generates an interpol... | 09/05/2006 |
| 7099580 | Method and system for communicating network topology in an optical communications network An exemplary embodiment of the invention is a network element in an optical communications network. The network element includes a data collection application program interface (API) for collecting topology information in a first format. A transport network bridge i... | 08/29/2006 |
| 7095801 | Phase adjustable polyphase filters A polyphase filter for wireless communication systems includes at least two phase splitting filters each having a variable resistance across their respective outputs. The variable resistance can take any suitable form, such as a MOS transistor biased in the linear (... | 08/22/2006 |
| 7088156 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 08/08/2006 |
| 7082293 | Adaptive radio transceiver with CMOS offset PLL An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged ... | 07/25/2006 |
| 7081788 | Band pass filter A band pass filter includes a first band pass filter constructed of a biquad circuit and having a first center frequency, and a second bandpass filter constructed of a biquad circuit and having a second center frequency different from the first center frequency, and... | 07/25/2006 |
| 7078950 | Delay-locked loop with feedback compensation A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is adjusted to minimize phase error, multiple clock cycles may be required before the adjusted signal is fed back... | 07/18/2006 |
| 7068086 | Phase correction circuit There is provided a phase correction circuit capable of detecting a skew between a data signal and a clock signal without requiring a clock signal as pattern data upon initialization. The phase correction circuit is configured to include a variable delay device 1... | 06/27/2006 |
| 7061307 | Current mirror compensation circuit and method A current compensation circuit for use with a current mirror is disclosed. The current mirror circuit has a current path defined by a first current mirror stage driving a second current mirror stage, the second current mirror stage is coupled to a supply voltage sou... | 06/13/2006 |
