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| Number | Title | Issue Date |
| 8169248 | Signal processing circuit and signal processing method A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplit... | 05/01/2012 |
| 8004336 | Semiconductor memory device and method for operating the same A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a pha... | 08/23/2011 |
| 7764103 | Phase error cancellation for differential signals In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage h... | 07/27/2010 |
| 7759997 | Multi-phase correction circuit A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another. ... | 07/20/2010 |
| 7446582 | Phase angle control method A method of phase angle control including the steps of generating a first periodic function having a first amplitude and generating a second periodic function having a second amplitude, which second periodic function is phase shifted relative to the first periodic f... | 11/04/2008 |
| 7443220 | Phase shift circuit and phase correcting method A phase shift circuit includes a 45° phase corrector that performs vector synthesis of signals supposed to have a 45° phase difference, out of a plurality of sets of orthogonal phase signals having an about 45° phase difference and an equal amplitude, the orthogo... | 10/28/2008 |
| 7436234 | Signal oversampling for improved S:N in reflector movement system Eight or more transition points are generated during a given period, and are used in tracking movement of an interferometer reflector. Duty cycles of generated square waves are used to establish precise intervals between the transition points, and precise wave-phase... | 10/14/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7342404 | Device for measurement and analysis of electrical signals of an integrated circuit component According to the invention, one or more external test connection contact points (pads; pins; balls), are provided in an integrated circuit component (chip) (1), through which signals (4, 5, 6) that are to be measured or analyzed are selectively fed, e.... | 03/11/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7321524 | Memory controller with staggered request signal output A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relati... | 01/22/2008 |
| 7319728 | Delay locked loop with frequency control A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry f... | 01/15/2008 |
| 7260168 | Network measurement method and apparatus The apparatus measures timing variations, such as the jitter or wander in a timing signal (100) of a telecommunications network. A recovered clock signal is sampled and digitized to produce a series of digital clock samples which are then processed (135 | 08/21/2007 |
| 7239575 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 07/03/2007 |
| 7231012 | Programmable frequency divider A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer ‘N’ provided at the input. In the normal mode the input is divided by the integer ‘N’. The divided output signal has... | 06/12/2007 |
| 7212057 | Measure-controlled circuit with frequency control A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based on the external signal. The delay locked circuit periodically performs... | 05/01/2007 |
| 7202725 | Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the ... | 04/10/2007 |
| 7194059 | Method and apparatus for skip-free retiming transmission of digital information A skip-free retiming system and method for transmission of digital information in a plesiochronous data communication system is described. The system is capable of supporting an unlimited number of retimers in serial data path between a first and a last node. The re... | 03/20/2007 |
| 7183828 | Shift clock generator, timing generator and test apparatus There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion... | 02/27/2007 |
| 7174475 | Method and apparatus for distributing a self-synchronized clock to nodes on a chip A method and apparatus are disclosed for dynamically reducing clock skew among various nodes on an integrated circuit. The disclosed clock skew reduction technique dynamically estimates the clock delay to each node and inserts a corresponding delay for each node suc... | 02/06/2007 |
| 7173503 | Multibit phase shifter with active and passive phase bits, and active phase bit therefor An RF phase shifter includes the cascade of active and passive RF phase shift bits, having different phase increments. The active phase shift bit includes a FET with source and drain. First and second RF single-pole, double throw switches have their common elements ... | 02/06/2007 |
| 7167034 | Arrangement for correcting the phase of a data sampling clock signal during a period of sampling data in a received signal In a clock phase corrector appropriately correcting the phase of a data sampling clock signal, a series of shift registers responds to respective sampling clock signals to store received data sequentially. The stored data are duplicated by a comparator register in r... | 01/23/2007 |
| 7138841 | Programmable phase shift and duty cycle correction circuit and method A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respe... | 11/21/2006 |
| 7123073 | Amplifier and frequency converter An amplifier circuit amplifies a differential signal supplied by a pair of input terminals. A phase controller circuit is placed between the emitters of two bipolar transistors and the ground. A feedback circuit is placed across the input and the output of the ampli... | 10/17/2006 |
| 7116252 | Encoder and signal adjustment method for the same An encoder includes: a detector; an A/D converter for performing A/D conversion for a two-phase analog signal output from the detector; an error correction circuit for correcting an error of the two-phase analog signal; an interpolation circuit for performing interp... | 10/03/2006 |
| 7110476 | Demodulation and modulation circuit and demodulation and modulation method A demodulation circuit and a demodulation method can optimize sampling timing with achieving reduction of power consumption. A preliminarily known signal is inserted in the digital transmission signal upon transmission. The demodulation circuit includes A/D converti... | 09/19/2006 |
| 7103108 | Digital signal processor transceiver A digital signal processor transceiver uses a finite impulse response filter memory to construct a phase integrated angle at each clock cycle. The FIR filter memory is addressed by a multibit pattern and a time count which are used in conjunction to determine the ad... | 09/05/2006 |
| 7092468 | Timing recovery system for a multi-pair gigabit transceiver A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog secti... | 08/15/2006 |
| 7057967 | Multi-mode synchronous memory device and methods of operating and testing same A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receivin... | 06/06/2006 |
| 7043392 | Interpolator testing system According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs... | 05/09/2006 |
| 7038518 | Method and apparatus for adjusting the phase and frequency of a periodic wave A delay circuit includes a phase vernier having a plurality of logic components. Each logic component includes a selectable injection input capable of adjusting a phase of an input to the phase vernier. ... | 05/02/2006 |
| 7034589 | Multi-stage delay clock generator The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signa... | 04/25/2006 |
| 7034595 | Multi-phase clock signal generators and methods of generating multi-phase clock signals A multi-phase clock signal generator provides multiple clock signals from an input clock signal, the multiple clock signals being inverted from one another and having substantially the same delay and duty cycle characteristics. Methods of generating multiple clock s... | 04/25/2006 |
| 7024576 | Network interface using programmable delay and frequency doubler A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal ... | 04/04/2006 |
| 6998885 | Apparatus and method for delay matching of full and divided clock signals A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state a... | 02/14/2006 |
| 6995593 | Circuit for programmable stepless clock shifting The present invention provides for a circuit for programmable stepless clock shifting, consisting of a splitter generating a 0° and a 90° shifted clocks from a reference clock, and an interpolator of the two shifted clocks, which provides at the output the desired... | 02/07/2006 |
| 6982578 | Digital delay-locked loop circuits with hierarchical delay adjustment Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers ha... | 01/03/2006 |
| 6958634 | Programmable direct interpolating delay locked loop Embodiments of the invention provide for a delay locked loop architecture including a coarse-fine type arrangement using one loop for non-continuous strobe that can be also be configured for continuous clocks as well. In particular, a reference loop establishes prec... | 10/25/2005 |
| 6950956 | Integrated circuit with timing adjustment mechanism and method An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which ... | 09/27/2005 |
| 6934866 | Network interface using programmable delay and frequency doubler A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal ... | 08/23/2005 |
