Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8130018 | Latch module and frequency divider A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elem... | 03/06/2012 |
| 7518428 | Phase compensation circuit and power circuit having same In a phase compensation circuit having a resistance connected to the output side of an error amplifier, a capacitor, and a conductance amplifier functioning as a capacitance amplifier circuit, capacitance is amplified by the conductance amplifier and used, whereby a... | 04/14/2009 |
| 7211967 | Strip light with constant current A strip light is disclosed. The light comprises an illuminating unit including a plurality of illuminators (e.g., LEDs) directly and electrically coupled in series, and a constant current stabilization unit with temperature compensating capability for supplying a co... | 05/01/2007 |
| 7193554 | Quantizer circuit According to an aspect of present invention, a quantizer is provided with reduced power consumption and area. Such a feature is attained by providing the input signal and a reference signal on input terminals of a pre-amplifier, and coupling the differential output ... | 03/20/2007 |
| 6977540 | High-speed isolated port A port isolator apparatus includes an optical isolator circuit that electrically isolates an input circuit from a high-speed output circuit. The input circuit uses a transistor to control the current flow of a data signal into the optical isolator. The optical isola... | 12/20/2005 |
| 6972624 | Low-voltage high dynamic range variable-gain amplifier Circuits and methods for providing a variable gain while powered from a low-voltage supply. In a specific embodiment, an input signal is converted to a current by an emitter-degenerated pair. A portion of the input current is discarded, while the remainder is variab... | 12/06/2005 |
| 6937080 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 08/30/2005 |
| 6218879 | S-R flip-flop circuit An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for... | 04/17/2001 |
| 5760626 | BICMOS latch circuit for latching differential signals A data value is passed from a bus (50) to a receiver (40) without a propagation delay. A data latch (10) stores the data value while the data value is being generated by the bus (50). The data latch (10) then holds the data value and provides the data val... | 06/02/1998 |
| 5751174 | Double edge triggered flip-flop A double edge triggered flip-flop is made up of six switches and four inverters. The input data is supplied to one end each of first and second ones of the six switches, the other ends of the first and second switches being separately connected to the inp... | 05/12/1998 |
| 5391935 | Assertive latching flip-flop An assertive latching flip-flop circuit is provided which prevents the occurrence of metastable outputs. The circuit comprises a single flip-flop which is comprised of standard switching transistors which are switched by a clocking mechanism having no add... | 02/21/1995 |
| 5389832 | Capacitively cross-coupled DCS emitter-follower output stage An output stage device for an enhanced differential current switch. The output stage receives a differential signal pair from a prior logic stage and must shift the output signals to the levels necessary for the next stage. The output stage has a differen... | 02/14/1995 |
| 5334887 | ECL latch circuit An ECL latch circuit includes a logic section and has a reset or set function. The logic section includes a first to seventh transistors. The third transistor has a collector connected to the collector of the first transistor, and a base for receiving a f... | 08/02/1994 |
| 5289055 | Digital ECL bipolar logic gates suitable for low-voltage operation Several digital bipolar logic circuits are described, for applications as digital logic gates and for buffering and level-shifting. These circuits are adapted for high-speed operation, and they have reduced supply-voltage requirements. In each of these ci... | 02/22/1994 |
| 5281865 | Flip-flop circuit A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corres... | 01/25/1994 |
| 5218249 | High speed, low forward voltage drop, SCR A silicon controlled rectifier device including an SCR portion controlled by an input voltage signal to a voltage comparator and having a latching circuit to permit the SCR portion to remain in the conducting state once switched even in the absence of the... | 06/08/1993 |
| 5212490 | Echo ranging system for detecting velocity and range of targets using composite doppler invariant-like transmissions with suppression of false targets False target (reverberation, clutter, etc.) detection is suppressed in an echo ranging system (sonar or radar) in which target velocity and range are measured using a composite Doppler invariant-like signal having at least two segments, such as are presen... | 05/18/1993 |
| 5212409 | Analog-to-digital converter latch circuit An analog-to-digital converter latching circuit functions alternatively in a degenerative mode and a regenerative mode. During degeneration, circuit stray capacitances are substantially discharged for resulting in fast operation. When the circuit switches... | 05/18/1993 |
| 5200650 | High frequency master/slave flip-flops A D-type, master/slave, flip-flop is described for use as a divide-by-2 frequency divider in which a frequency to be divided is input as a clock signal and the Q output is connected to the D input, and in which the master section and the slave section con... | 04/06/1993 |
| 5172011 | Latch circuit and method with complementary clocking and level sensitive scan capability Latch circuit and method which permit two-phase latches and flip-flops to be intermixed in a system having level sensitive scanning without critical clock requirements. The circuit includes a master latch having a normal data input and a scan data input, ... | 12/15/1992 |
| 5170074 | Master-slave clocked flip-flop circuit A flip-flop of a master-slave type of a CMOS structure having no P channel transistor between nodes of the master flip-flop and of the slave flip-flop is provided. Only one P channel MOS transistor is existent in a route of the current controlling a rise ... | 12/08/1992 |
| 5134312 | Shared current source for alpha particle insensitive bipolar latch A bipolar ECL latch or flip-flop circuit of the isolated differential feedback type provides a high level of alpha particle immunity, without unduly affecting the propagation delay, power dissipation or circuit area in an integrated circuit device. A pair... | 07/28/1992 |
| 5079452 | High speed ECL latch with clock enable An ECL latch having a clock enable is provided with a first current source for the latch and a second current source for the clock enable. The latch alternates between a latch mode and a transparent mode under the control of a CLOCK signal. The clock enab... | 01/07/1992 |
| 5001361 | Master-slave flip-flop circuit A master-slave flip-flop circuit is made up of a master part which holds a data signal responsive to a clock signal and outputs the held data signal in the form of complementary output signals, and a slave part which holds the complementary output signals... | 03/19/1991 |
| 4996445 | Disturbance resistant data storage circuit An improved disturbance resistant data storage circuit having a further transistor for each one of a pair of input transistors, the cross-coupled transistors, and the output transistors which are paired therewith.... | 02/26/1991 |
| 4975595 | Scannable register/latch circuit A circuit is described for functioning as a transparent latch, a latch where the data is determined by the state of a data signal at the time a signal changes state, a D-type flip-flop, and a scan path element. The mode of operation of the circuit is dete... | 12/04/1990 |
| 4974241 | Counter employing exclusive NOR gate and latches in combination The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flo... | 11/27/1990 |
| 4943741 | ECL/CML emitter follower current switch circuit An emitter follower current switch circuit is provided for emitter coupled logic or current mode logic (ECL/CML) circuits having output buffer emitter follower transistor elements which source true and complementary output signals of high and low potentia... | 07/24/1990 |
| 4928024 | Referenceless ECL logic circuit An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the... | 05/22/1990 |
| 4779011 | Latch circuit having two hold loops A latch circuit has two complementary hold loops therein for improving noise tolerance. The latch circuit includes a first gate for receiving a data and a first clock signal and outputting a first signal in response to a change in the clock signal. A seco... | 10/18/1988 |
| 4754173 | Emitter coupled logic latch with boolean logic input gating network A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock... | 06/28/1988 |
| 4754171 | High speed low power emitter coupled logic circuit A current-mode logic circuit includes a pair of input bipolar transistors coupled in the emitter-coupled single differential circuit configuration, one of which input transistors is connected at its base to receive an input signal and the other input tran... | 06/28/1988 |
| 4743781 | Dotting circuit with inhibit function A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the colle... | 05/10/1988 |
| 4628216 | Merging of logic function circuits to ECL latch or flip-flop circuit A combination circuit formed of a functional portion circuit coupled to a latch or flip-flop circuit portion which is fabricated as a single gate on an integrated circuit semiconductor chip. The functional circuit portion can be a multiplexer, or other lo... | 12/09/1986 |
| 4622475 | Data storage element having input and output ports isolated from regenerative circuit A data storage element having input and output ports isolated from a regenerative latch portion so that the data transmission path is not through the latch. The circuit arrangement provided greatly reduces the probability of a metastable occurrence and pe... | 11/11/1986 |
| 4553046 | Monolithically integratable bistable multivibrator circuit having at least one output that can be placed in a preferential state A bistable multivibrator circuit includes two main transistors and two other transistors and an additional pair of transistors. The multivibrator circuit can be monolithically integrated and has an output that can be placed in a preferential state. The tw... | 11/12/1985 |
| 4528465 | Semiconductor circuit alternately operative as a data latch and a logic gate A high speed latch for integrated circuit applications employs a linear differential logic type gate and a cross coupled differential pair storage element which share common load terminals. The cross coupled differential pair is transparent to the operati... | 07/09/1985 |
| 4378505 | Emitter function logic latch and counter circuits An EFL D-type latch employing an EFL storage cell (17) controlled by a two-level tree of differential transistor pairs (12, 14 and 32, 34). Also described are counter cells, up counters, down counters and up/down counters, including binary, hexadecimal an... | 03/29/1983 |
| 4274017 | Cascode polarity hold latch having integrated set/reset capability An improved polarity hold latch is described having a set and reset capability integrated therein. As implemented, this latch provides the desired logical functions at a reduced circuit cost and power requirements. At the same time, it overcomes the need ... | 06/16/1981 |
| 4237387 | High speed latching comparator A window comparator latch network is disclosed for track or sampling a differential input signal and for "latching" the input signal upon a clock signal. Several latch networks are disclosed for both single and dual differential input configurations. The ... | 12/02/1980 |
