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Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 8049546 | Flip-flop, frequency divider and RF circuit having the same A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output... | 11/01/2011 |
| 7375568 | Logic circuit with restrained leak current to differential circuit In the present invention, a logic circuit is provided therein with a current supply control circuit for controlling the amount of current supplied to a differential circuit. This current supply control circuit comprises a bypass path for bypassing the current around... | 05/20/2008 |
| 7365596 | State retention within a data processing system Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when ... | 04/29/2008 |
| 7356785 | Optimizing IC clock structures by minimizing clock uncertainty A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a ... | 04/08/2008 |
| 7319310 | Regulated power supply unit An improved power supply unit includes a DC power source having a positive terminal and a negative terminal, and a voltage regulating circuit that includes a plurality of elements coupled in series between the positive and negative terminals of the DC power source t... | 01/15/2008 |
| 7253661 | Method and apparatus for a configurable latch A configurable latch is implemented using a configurable pulse generator and a level sensitive (LS) latch. The configurable pulse generator produces either a pulse signal that is aligned with the input clock edge, or simply provides the input clock signal to its out... | 08/07/2007 |
| 7215594 | Address latch circuit of memory device An address latch circuit of a memory device is disclosed. A latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possibl... | 05/08/2007 |
| 7215169 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 05/08/2007 |
| 7202645 | Regulated power supply unit An improved power supply unit includes a DC power source having a positive terminal and a negative terminal, and a voltage regulating circuit that includes a plurality of elements coupled in series between the positive and negative terminals of the DC power source t... | 04/10/2007 |
| 7079617 | Shift register and driving method thereof A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputt... | 07/18/2006 |
| 7038516 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 05/02/2006 |
| 6982583 | Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 01/03/2006 |
| 6965151 | Device including a resistive path to introduce an equivalent RC circuit Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the dev... | 11/15/2005 |
| 6937102 | Low bias current/temperature compensation current mirror for linear power amplifier A power amplifier circuit whose performance is optimized by operating its stages in substantially close to a Class B mode by reducing quiescent current during low driver signal levels. As the driver signal amplitude increases, the operation of the amplifier is confi... | 08/30/2005 |
| 6911855 | Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 06/28/2005 |
| 6897697 | Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 05/24/2005 |
| 6891419 | Methods and apparatus for employing feedback body control in cross-coupled inverters In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with ... | 05/10/2005 |
| 6847245 | High-speed, current driven latch A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the ... | 01/25/2005 |
| 6737889 | Method for increasing the power efficiency and noise immunity of clocked full-rail differential logic Clocked full-rail differential logic circuits are provided with shut-off devices. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large pre-charge high or “dip” experienced by prior a... | 05/18/2004 |
| 6714053 | Fast set reset latch with complementary outputs having equal delay and duty cycle For use in a strobed comparator circuit of the type comprising a decision circuit and a set-reset (SR) latch for holding an output of the decision circuit, an apparatus and method is disclosed for reducing output delay between two complementary output signals of the... | 03/30/2004 |
| 6614274 | 2/3 full-speed divider using phase-switching technique A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pai... | 09/02/2003 |
| 6614276 | Flip-flop design A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30. Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29. Latch circuit 30 comprises an inverter 31 and a tristate NOR gate 32. When the CLK (clock input ... | 09/02/2003 |
| 6542016 | Level sensitive latch A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled t... | 04/01/2003 |
| 6535042 | High-speed, current-driven latch A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the la... | 03/18/2003 |
| 6509772 | Flip-flop circuit with transmission-gate sampling A flip-flop circuit comprising a first stage having a transmission gate to receive a data signal from an input node, and a second stage connected to the first stage, the second stage having another transmission gate to transfer the data signal to a memory... | 01/21/2003 |
| 6492856 | Edge triggered latch with symmetrical paths from clock to data outputs A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used t... | 12/10/2002 |
| 6489810 | Highly reliable programmable monostable An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and... | 12/03/2002 |
| 6424195 | Dynamic flop with power down mode A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has... | 07/23/2002 |
| 6424194 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, ... | 07/23/2002 |
| 6400206 | Dual-level voltage shifters for low leakage power A dual level voltage shifter includes several series connections of transistors, and cross coupled pairs of transistors, to provide dual-level voltage shifting with low power consumption and low static current. In another embodiment, a dual level voltage ... | 06/04/2002 |
| 6373310 | Scalable set/reset circuit with improved rise/fall mismatch A multiple input set/reset circuit is described that includes cross-coupled inverters connected between set and reset nodes. The set/reset circuit also includes at least one set input circuit coupled to the set node configured to receive a set signal and ... | 04/16/2002 |
| 6310500 | Race removal or reduction in latches and loops using phase skew A method for resolving race conflicts in a loop circuit having a forward path and a feedback path includes enabling and disabling the feedback path in accordance with a phase waveform. The phase waveform may be a system clock, in which case one of two app... | 10/30/2001 |
| 6225846 | Body voltage controlled semiconductor integrated circuit A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connec... | 05/01/2001 |
| 6087872 | Dynamic latch circuitry A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop... | 07/11/2000 |
| 6084459 | Voltage level shifting circuit An improved voltage level shifting circuit which is capable of increasing a level shifting speed and reducing a current consumption and layout area by decreasing a pull-up capacity of the pull-up PMOS transistors in a side in which a voltage level is shif... | 07/04/2000 |
| 6031403 | Pull-up and pull-down circuits According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a ... | 02/29/2000 |
| 6011421 | Scalable level shifter for use in semiconductor memory device A scalable level shifter which performs at high-speeds and optimizes power consumption. The scalable level shifter receives an input signal and converts the input signal having a scalable voltage level to an output signal having a predetermined voltage le... | 01/04/2000 |
| 5999029 | Meta-hardened flip-flop A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is... | 12/07/1999 |
| 5952860 | Amplifier using a single polarity power supply The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the ampl... | 09/14/1999 |
| 5903175 | D-type latch circuit and device using the same A D-type latch circuit includes a first differential amplifier circuit which receives first and second input signals having a complementary relationship and has an active state in a transfer operation and an inactive state in a latch operation. A second d... | 05/11/1999 |
