Bizarre Patents
A Receptacle for supporting, rotating and sculpting a portion of ice cream or similarly malleable food while it is being consumed.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8188780 | Pulsed static flip-flop A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a... | 05/29/2012 |
| 8004334 | Data latch circuit and electronic device The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the othe... | 08/23/2011 |
| 7999590 | Level-converting flip-flop and pulse generator for clustered voltage scaling Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and gener... | 08/16/2011 |
| 7915940 | Differential latch, differential flip-flop, LSI, differential latch configuration method, and differential flip-flop configuration method A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connecte... | 03/29/2011 |
| 7876142 | Latch inverter and flip-flop using the same A latch inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first level-adjusting unit and a second level-adjusting unit. The first level-adjusting unit changes the voltage level of the source of ... | 01/25/2011 |
| 7872514 | Latch circuit and clock signal dividing circuit Latch circuit and clock signal dividing circuit comprises sequentially connected latch circuits. Each latch circuit has D-type latch with latch clock input, data input and data output. A difference detector is coupled to D-type latch, and has a difference output tha... | 01/18/2011 |
| 7855587 | Asymmetric sense-amp flip-flop An Asymmetric Sense-Amp Flip-Flop (ASAFF) is disclosed that may achieve zero setup time and short clock-to-Q delays. The ASAFF captures input data at a clock transition by setting values of a first node and a second node in a manner that is input data value dependen... | 12/21/2010 |
| 7816964 | Pulse operated flip-flop circuit having test-input function and associated method The pulse generation circuit generates a first pulse signal and a complementary second pulse signal. The first and second pulse signals are activated simultaneously in a normal mode and activated selectively in response to a test input signal in a test mode. A multi... | 10/19/2010 |
| 7759996 | Storage elements using nanotube switching elements Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, ma... | 07/20/2010 |
| 7746140 | Scannable latch A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signal... | 06/29/2010 |
| 7737749 | Elastic pipeline latch with a safe mode An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an input signal through as an output signal, and a pulse width/inhibit ... | 06/15/2010 |
| 7733145 | Nonvolatile latch circuit and nonvolatile flip-flop circuit A nonvolatile latch circuit includes: a first gate part controlling to load or intercept an input signal based on a gate signal; a first logic gate functioning as an inverter or a gate outputting a constant voltage in response to the first control signal; a second l... | 06/08/2010 |
| 7719337 | Semiconductor device A semiconductor device includes a circuit having a first data holding node and a second data holding node; a first MOS field-effect transistor coupled to the first data holding node; a second MOS field-effect transistor coupled to the second data holding node; and a... | 05/18/2010 |
| 7710177 | Latch device having low-power data retention A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the l... | 05/04/2010 |
| 7692466 | Sense amplifier based flip-flop A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to genera... | 04/06/2010 |
| 7671652 | Logic circuit for use in a latch circuit and a data reading circuit or the like which includes such a latch circuit A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first trans... | 03/02/2010 |
| 7671653 | Dual edge triggered flip flops An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on... | 03/02/2010 |
| 7659762 | Clock synchronizer Disclosed herein are synchronization latch solutions. ... | 02/09/2010 |
| 7656211 | Dynamic floating input D flip-flop A dynamic floating input D flip-flop (DFIDFF) is provided. The DFIDFF includes a floating input stage, a first string of transistors, and a second string of transistors. At a pre-charge period, the floating input stage transmits the input data to the first string of... | 02/02/2010 |
| 7649396 | Soft error rate hardened latch A latch is provided that includes a first inverter, a second inverter, a first latch circuit and a second latch circuit. The first inverter to receive the first clock signal from an input port and to provide a clock signal. The second inverter to receive the first c... | 01/19/2010 |
| 7583123 | High-speed flip-flop circuit A flip-flop circuit that captures an input signal in sync with a clock, has a first gate outputting a first signal corresponding with input signal; a second gate generating a second signal of a first predetermined level in response to a first level of clock and caus... | 09/01/2009 |
| 7576583 | Single-event effect tolerant latch circuit and flip-flop circuit Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-p... | 08/18/2009 |
| 7548103 | Storage device having low power mode and methods thereof A storage device and methods thereof are disclosed. The device includes a clock control module and a latch. During normal operation, the clock control module provides a periodic clock signal to a clock input of the latch, allowing the latch to operate normally. In a... | 06/16/2009 |
| 7518427 | Apparatus, system, and method for hardened latch Various embodiments include a latch having a node to receive input information, and a first pseudo-inverter with a first input node, a second input node, and an output node to generate output information based on information at the first and second input nodes. The ... | 04/14/2009 |
| 7514976 | Pulsed flip-flop and method of controlling the same A pulsed flip-flop capable of adjusting a pulse width according to an operating voltage includes: a flip-flop operating in synchronization with a pulse signal; a pulse generating circuit generating the pulse signal in response to a clock signal; and a pulse width co... | 04/07/2009 |
| 7504871 | Flip-flops and electronic digital circuits including the same A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first ... | 03/17/2009 |
| 7501871 | Latch circuit A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D−). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q−). One of the outputs (Q−) is coupled to... | 03/10/2009 |
| 7492203 | High speed flip-flops and complex gates using the same In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and ... | 02/17/2009 |
| 7489174 | Dynamic flip-flop circuit A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within... | 02/10/2009 |
| 7479818 | Sense amplifier flip flop A sense amplifier flip flop including a differential input portion, a differential amplifying portion including a first inverter and a second inverter, and a bias voltage generating portion. The bias voltage generating portion is configured to generate body voltages... | 01/20/2009 |
| 7456669 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a comparator for making a comparison between a logical value of an input signal and a logical value of an output signal and outputting a combination signal having a combination of the logical values; and a flip-flop... | 11/25/2008 |
| 7453300 | MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop, a circuit including the MTCMOS flip-flop, and a method of forming the MTCMOS flip-flop are disclosed. The MTCMOS flip-flop breaks a leakage current path during a sleep mode to reta... | 11/18/2008 |
| 7443218 | Semiconductor integrated circuit with pulsed clock data latch A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latc... | 10/28/2008 |
| 7439775 | Sense amplifier circuit and sense amplifier-based flip-flop having the same A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluatio... | 10/21/2008 |
| 7440534 | Master-slave flip-flop, trigger flip-flop and counter A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-sl... | 10/21/2008 |
| 7425855 | Set/reset latch with minimum single event upset A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in... | 09/16/2008 |
| 7420403 | Latch circuit and flip-flop A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit is presented that uses both low and high threshold inverters. The multi-threshold latch circuit includes: a low threshold forward clock inverter inverting an input-termi... | 09/02/2008 |
| 7417470 | Phase frequency detector with a novel D flip flop Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configuration for a D type flip flop is ... | 08/26/2008 |
| 7417466 | Flip-flop circuit and frequency divider using the flip-flop circuit In a flip-flop circuit where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the conductivity of a first load transistor connected to the first output terminal is controlled by the signa... | 08/26/2008 |
| 7414449 | Dynamic scannable latch and method of operation A latch has a first mode in which the latch functions as a dynamic latch and a second mode in which the latch functions as a static latch. The latch has a feedback circuit that in turn has two parallel switchable loads. The first load is responsive to a data input s... | 08/19/2008 |
