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| Number | Title | Issue Date |
| 8134395 | Leakage power optimized structure A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. ... | 03/13/2012 |
| 8093935 | Logic circuit A logic circuit includes two two-terminal switching devices and receives first and second pulses as inputs. Each of the two devices has two different stable resistivity values for each applied voltage that is greater than a first threshold voltage (Vth1) and ... | 01/10/2012 |
| 7948291 | Logic circuit The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, wher... | 05/24/2011 |
| 7902895 | Semiconductor device equipped with a pull-down circuit Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor... | 03/08/2011 |
| 7683688 | High performance clocked latches and devices therefrom An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch node (420) positioned between a first pull up device (416) and a f... | 03/23/2010 |
| 7439775 | Sense amplifier circuit and sense amplifier-based flip-flop having the same A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluatio... | 10/21/2008 |
| 7425855 | Set/reset latch with minimum single event upset A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in... | 09/16/2008 |
| 7358787 | Dual operational mode CML latch A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal ... | 04/15/2008 |
| 7352215 | High speed latch comparators In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and appli... | 04/01/2008 |
| 7339403 | Clock error detection circuits, methods, and systems Clock error detections circuits can detect clock duty cycle error and/or quadrature phase error. During an evaluation phase, capacitors are charged. During an evaluation phase, the capacitors are unequally discharged based on the error. A positive feedback mechanism... | 03/04/2008 |
| 7315191 | Digital storage element architecture comprising dual scan clocks and reset functionality A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first tran... | 01/01/2008 |
| 7312627 | Decoding circuit for on die termination in semiconductor memory device and its method A decoding circuit of an on die termination (ODT) control signal for stably performing an ODT operation. The decoding circuit includes: a latch unit for receiving a plurality of input signals and for holding previous output signals of the latch unit when the plurali... | 12/25/2007 |
| 7301362 | Duplicated double checking production rule set for fault-tolerant electronics Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The... | 11/27/2007 |
| 7301382 | Data latch circuit and electronic device The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the othe... | 11/27/2007 |
| 7274234 | Digital storage element architecture comprising integrated multiplexer and reset functionality A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional... | 09/25/2007 |
| 7233172 | Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude A differential amplifier circuit has a latch unit and a differential input portion. A minute current is kept to flow through the differential input portion. Therefore, the differential amplifier circuit can accurately amplify even a signal high in speed and small in... | 06/19/2007 |
| 7231533 | Wake-up reset circuit draws no current when a control signal indicates sleep mode for a digital device A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused un... | 06/12/2007 |
| 7215170 | Low voltage logic circuit with set and/or reset functionality A low voltage logic circuit with asynchronous SET and/or RESET functions is described herein. The low voltage logic circuit may be primarily used in forming low voltage flip-flop circuits, but may also be used to form multiplexers and other logic configurations. The... | 05/08/2007 |
| 7212040 | Stabilization of state-holding circuits at high temperatures A state-holding circuit having improved stability at high temperatures includes a bi-stable circuit capable of assuming one of two reversible and stable states. The bi-stable circuit comprises a plurality of logic components (e.g., transistors) arranged into two sid... | 05/01/2007 |
| 7199650 | Method and apparatus for reducing interference A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current,... | 04/03/2007 |
| 7199638 | High speed voltage level translator A high speed voltage level translator having minimum power dissipation and reduced area, specifically in the sub 0.1 micron domain, includes a transistorized arrangement to receive a low voltage input signal and to control current in the translated high level voltag... | 04/03/2007 |
| 7193444 | High speed data bit latch circuit A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s1, a NAND circuit having a first input connected to signal s1, a second input connect... | 03/20/2007 |
| 7194673 | Detecting intermittent losses of synchronization in a fibre channel loop Described are a storage system and method for detecting an intermittent loss of synchronization in communication signals received by an enclosure connected to a Fibre Channel loop. A control board produces a first signal representing a status of communication signal... | 03/20/2007 |
| 7180349 | Frequency divider system A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which op... | 02/20/2007 |
| 7176736 | High-speed, current driven latch A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the ... | 02/13/2007 |
| 7177182 | Rewriteable electronic fuses Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predet... | 02/13/2007 |
| 7173465 | High-speed, current-driven latch A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the ... | 02/06/2007 |
| 7154319 | Pulse-based high-speed low-power gated flip-flop circuit A high-speed gated flip-flop includes a latch configured to generate a data output signal (Q) in response to a data input signal (D) and a pair of true and complementary clock pulses (GCP,GCPB). These clock pulses are provided by a clock generator responsive to a pe... | 12/26/2006 |
| 7149874 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 12/12/2006 |
| 7145370 | High-voltage switches in single-well CMOS processes Circuits are provided for high-voltage switching in single-well CMOS processes. ... | 12/05/2006 |
| 7142030 | Data latch circuit and electronic device The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the othe... | 11/28/2006 |
| 7136958 | Multiple processor system and method including multiple memory hub modules A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors ... | 11/14/2006 |
| 7126398 | Method and an apparatus to generate static logic level output A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The app... | 10/24/2006 |
| 7126858 | Apparatus for emulating asynchronous clear in memory structure and method for implementing the same Circuitry is disclosed for emulating asynchronous clear on each of a read address register of a memory cell and a data output register of a memory cell such that the memory cell can be defined in a memory structure that does not support asynchronous clear capability... | 10/24/2006 |
| 7123069 | Latch or phase detector device The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may als... | 10/17/2006 |
| 7109772 | D-type flipflop A flipflop having a clock input for applying a clock signal, a data input for applying a data signal, a noninverting output and an inverting output, where the flipflop has a first holding element with a first feedback loop and a second holding element with a second ... | 09/19/2006 |
| 7084683 | High-speed differential flip-flop with common-mode stabilization A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first curr... | 08/01/2006 |
| 7068080 | Method and apparatus for reducing power consumption within a logic device Method and apparatus for reducing power consumption within a logic device is described. A logic device comprises a clock gate and a flip-flop. The clock gate includes a clock enable terminal and a clock terminal. The flip-flop includes an input terminal, an output t... | 06/27/2006 |
| 7057180 | Detector for alpha particle or cosmic ray A detector circuit and method for detecting a silicon well voltage or current to indicate an alpha particle or cosmic ray strike of the silicon well. One significant application for the detection circuit of the present invention is for the redundancy repair latches ... | 06/06/2006 |
| 7053652 | Static memory cell circuit with single bit line and set/reset write function Static memory cell circuits having a single bit line further include first and second word lines, first and second cross-coupled logic gates, and first and second pass gates. The first pass gate is coupled between the bit line and a first storage node at the output ... | 05/30/2006 |
