Quotables
"Telephone, n. An invention of the devil which abrogates some of the advantages of making a disagreeable person keep his distance. "
Ambose Bierce
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8143930 | Method and apparatus for amplifying a time difference Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an output device of the time amplifier. ... | 03/27/2012 |
| 7612594 | Latch circuit and semiconductor integrated circuit having the same A latch circuit includes first, second, and third inverter circuits, a switching element, and a capacitor element. The first inverter circuit and the second inverter circuit are cross-connected to each other. The third inverter circuit logically inverts an output fr... | 11/03/2009 |
| 7369450 | Nonvolatile memory having latching sense amplifier and method of operation A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharg... | 05/06/2008 |
| 7365596 | State retention within a data processing system Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when ... | 04/29/2008 |
| 7358787 | Dual operational mode CML latch A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal ... | 04/15/2008 |
| 7355534 | Serial-to-parallel conversion circuit, and semiconductor display device employing the same In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency ... | 04/08/2008 |
| 7336114 | High-speed latching technique and application to frequency dividers The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared ... | 02/26/2008 |
| 7333924 | Method and system for device level simulation of large semiconductor memories and other circuits A method for device level simulation of a circuit modeled by a set of CCR graphs, a computer system programmed to perform such a method, and a computer readable medium which stores code for implementing such a method. Typically, the circuit includes MOS transistors ... | 02/19/2008 |
| 7301373 | Asymmetric precharged flip flop A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Dep... | 11/27/2007 |
| 7278074 | System and shadow circuits with output joining circuit In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a... | 10/02/2007 |
| 7265582 | Level shifter A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by r... | 09/04/2007 |
| 7265599 | Flipflop that can tolerate arbitrarily slow clock edges A edge triggered flipflop tolerates arbitrarily slow clock edge rates by utilizing complex gates, with weighted transistors, to electrically isolate the master latch from the data inputs, before the master latch and the slave latch are electrically connected togethe... | 09/04/2007 |
| 7262648 | Two-latch clocked-LSSD flip-flop A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches. ... | 08/28/2007 |
| 7248665 | Prescaler Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof bei... | 07/24/2007 |
| 7236031 | Fast bistable circuit protected against random events A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an out... | 06/26/2007 |
| 7215594 | Address latch circuit of memory device An address latch circuit of a memory device is disclosed. A latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possibl... | 05/08/2007 |
| 7187222 | CMOS master/slave flip-flop with integrated multiplexor A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pu... | 03/06/2007 |
| 7187211 | P-domino output latch A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at lea... | 03/06/2007 |
| 7187210 | P-domino register A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data sig... | 03/06/2007 |
| 7187205 | Integrated circuit storage element having low power data retention and method therefor A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a ... | 03/06/2007 |
| 7183808 | Circuit for power management of standard cell application A power management circuit for logic cells. A logic cell is operated in normal or standby modes according to a power control signal. The logic cell includes an output terminal and a power input terminal. A switch is coupled between a power voltage, the power control... | 02/27/2007 |
| 7183827 | Mixing prevention circuit for preventing mixing of semiconductor chips and semiconductor chip discrimination method First, second, and third inverters are connected in series. An output of the third inverter is supplied to the gates of first pMOS and nMOS. An output of the first inverter is supplied to the gate of the second nMOS and the drain of the second nMOS is connected to t... | 02/27/2007 |
| 7183795 | Majority voter apparatus, systems, and methods Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs. ... | 02/27/2007 |
| 7164612 | Test circuit for measuring sense amplifier and memory mismatches Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed ... | 01/16/2007 |
| 7158404 | Power management circuit and memory cell A circuit for power management of a memory cell. A first power switch is coupled between a power voltage, the power control signal and the memory cell. The first power switch is turned off to disconnect the power voltage and the memory cell when the power control si... | 01/02/2007 |
| 7132848 | Power management circuit A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of da... | 11/07/2006 |
| 7126398 | Method and an apparatus to generate static logic level output A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The app... | 10/24/2006 |
| 7123069 | Latch or phase detector device The invention relates to a circuit device, into which a first signal and a second signal are input, wherein a first switching array is provided, by means of which it is determined which of the two signals, is the first to change its state. The circuit device may als... | 10/17/2006 |
| 7084683 | High-speed differential flip-flop with common-mode stabilization A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first curr... | 08/01/2006 |
| 7082560 | Scan capable dual edge-triggered state element for application of combinational and sequential scan test patterns An apparatus and method of scanning a dual edge-triggered flip-flop with scan capability includes a first scan slave element capable of capturing data on a positive edge of a clock signal; and a second scan slave element capable of capturing data on a negative edge ... | 07/25/2006 |
| RE39154 | Integrated circuit In an integrated circuit, a time-axis expanding circuit is provided in addition to a driver circuit for outputting a signal outside. The time-axis expanding circuit has an equivalent receiver circuit similar to an ordinary receiver circuit, and a D-type flip-flop ci... | 07/04/2006 |
| 7057421 | Flipflop A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals ... | 06/06/2006 |
| 7042262 | System and method for providing a fast and power efficient jam latch A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of ... | 05/09/2006 |
| 7028069 | Dynamic circuit using exclusive states The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of ... | 04/11/2006 |
| 7019575 | Mixing prevention circuit for preventing mixing of semiconductor chips and semiconductor chip discrimination method First, second, and third inverters are connected in series. An output of the third inverter is supplied to the gates of first pMOS and nMOS. An output of the first inverter is supplied to the gate of the second nMOS and the drain of the second nMOS is connected to t... | 03/28/2006 |
| 6998884 | Circuit for auto-clamping input pins to a definite voltage during power-up or reset An auto-grounding circuit responsive to a reset signal discharges an input terminal of an integrated circuit and its associated input line to ground, using a pull-down transistor coupled to the input line, with a gate of the pull-down transistor coupled to receive t... | 02/14/2006 |
| 6943605 | Scan cell designs for a double-edge-triggered flip-flop According to some embodiments, scan cell designs are provided for a double-edge-triggered flip-flop. ... | 09/13/2005 |
| 6940313 | Dynamic bus repeater with improved noise tolerance In an embodiment, a dynamic bus includes a dynamic bus repeater with a noise margin of about Vcc/2. The bus repeater splits the bus into front and rear segments. The front segment pre-charges while the rear segment evaluates, and vice versa. The dynamic bus repeater... | 09/06/2005 |
| 6937080 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 08/30/2005 |
| 6927619 | Method and system for reducing leakage current in integrated circuits using adaptively adjusted source voltages An apparatus for reducing leakage currents in an integrated circuit having logic gates containing PMOS devices and NMOS devices. The apparatus comprises a power management unit capable of: i) applying a fixed VDD supply voltage to body connections of said PMOS devic... | 08/09/2005 |
