Quotables
"The production of too many useful things results in too many useless people."
Karl Marx
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7759995 | Semiconductor integrated circuit with a logic circuit including a data holding circuit A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit t... | 07/20/2010 |
| 7391249 | Multi-threshold CMOS latch circuit Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal... | 06/24/2008 |
| 7265582 | Level shifter A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by r... | 09/04/2007 |
| 7183673 | Passive inductive switch A passive inductive switch for coupling a battery to a load in a remotely deployed battery-powered electronic device. The switch operates in response to a transmitted magnetic field at a particular frequency. The switch includes an antenna for transforming the magne... | 02/27/2007 |
| 7016664 | Mixer circuit arrangement and an image-reject mixer circuit arrangement A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is ... | 03/21/2006 |
| 6937080 | Current-controlled CMOS logic family Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, X... | 08/30/2005 |
| 6759876 | Semiconductor integrated circuit The semiconductor integrated circuit of this invention includes a first transistor for setting a first node at a first logic level in accordance with a clock signal; an input circuit for setting the first node at a second logic level in accordance with an input sign... | 07/06/2004 |
| 6742858 | Label printer-cutter with mutually exclusive printing and cutting operations A label printer-cutter includes a frame and a print head assembly connected to the frame. The print head assembly includes a print head for printing to a label media. The label printer-cutter includes a cutting assembly connected to the frame, and the cutting assemb... | 06/01/2004 |
| 6670837 | Time domain reflectometer with digitally generated variable width pulse output A pulse generator includes circuitry for starting a pulse in response to receipt of a pulse enable signal. The pulse enable signal is synchronous with a first time base. The pulse generator includes circuitry for ending the pulse after a predetermined, us... | 12/30/2003 |
| 6646474 | Clocked pass transistor and complementary pass transistor logic circuits A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled ... | 11/11/2003 |
| 6605971 | Low voltage latch Low voltage latches are designed such that the latch components are comprised of low threshold transistors. To overcome the effects of leakage current and ensure proper latch operation, according to the invention, the channel widths of the low threshold t... | 08/12/2003 |
| 6522184 | Flip-flop circuit In a flip-flop circuit, a master latch has a data input circuit that reads data when a clock input signal is at a first level. When the clock input signal is at a second level, a first data holding circuit holds the data, and a signal switching circuit tr... | 02/18/2003 |
| 6462582 | Clocked pass transistor and complementary pass transistor logic circuits A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled ... | 10/08/2002 |
| 6441648 | Double data rate dynamic logic A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide ... | 08/27/2002 |
| 6426658 | Buffers with reduced voltage input/output signals A buffer circuit that operates with reduced voltage input and output signals receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is from 0 volts to VRED,... | 07/30/2002 |
| 6404254 | Latch circuit and semiconductor integrated circuit having the latch circuit with control signal having a large voltage amplitude A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a low power consumption, includes a latch circuit characterized in that as the control signal a clock sign... | 06/11/2002 |
| 6388489 | Large input function replaying dynamic entry latch with static and monotonic dual rail outputs An a new dynamic logic entry latch or new "ELAT" and a method to capture a static input and convert it to a single rail dynamic signal with improved functionality and reduced clock and input load. The new ELAT utilizes a pulsed evaluate concept to enable ... | 05/14/2002 |
| 6369629 | Flip-flop circuit In a flip-flop circuit, a master latch has a data input circuit that reads data when a clock input signal is at a first level. When the clock input signal is at a second level, a first data holding circuit holds the data, and a signal switching circuit tr... | 04/09/2002 |
| 6346836 | Synchronizing stage A synchronizing stage for synchronizing asynchronous signals provides for a signal stage to be connected in parallel with a clocked input stage and a holding stage that is clocked in anti-phase. The signal stage is clocked in anti-phase with the input sta... | 02/12/2002 |
| 6285227 | Latch ratio circuit with plural channels The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one s... | 09/04/2001 |
| 6204652 | Voltage regulating system for electrical loads in a motor vehicle A motor vehicle electrical system has at least one apparatus for regulating the power supply voltage of an electrical load which has a nominal or rated supply voltage. The regulating apparatus is supplied by a variable value unidirectional voltage source.... | 03/20/2001 |
| 6172539 | Synchronous buffer circuit and data transmission circuit having the synchronous buffer circuit A first latch circuit latches output data in response to a leading edge of a clock signal. A second latch circuit latches the output data in response to a trailing edge of the clock signal. When the first latch circuit latches a low level, an n-channel MO... | 01/09/2001 |
| 6107852 | Method and device for the reduction of latch insertion delay A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main l... | 08/22/2000 |
| 6052009 | D-type flipflop A flipflop, which is realized in an ECL or CML technique, has an internal output for the logic signal in a symmetrical mode and is provided with two transistor followers for supplying the two output signal components from the internal output, and each of ... | 04/18/2000 |
| 6008679 | Semiconductor integrated circuit and semiconductor input system A Schmitt trigger circuit has an input device and an amplifier. The input device has a current adder device having a P-type current mirror circuit and a N-type current mirror circuit connected in parallel. The P-type current mirror circuit has a positive ... | 12/28/1999 |
| 5949265 | Soft latch circuit having sharp-cornered hysteresis characteristics A soft latch circuit having a first and second inverter is disclosed. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The first inver... | 09/07/1999 |
| 5838152 | Pulse timer circuit A pulse timer circuit comprising a monostable multivibrator which includes two complementary transistors Q5, Q6, has the advantage of good tolerance to temperature fluctuation owing to the provision of a Schottky diode D4 connected between the emitter and... | 11/17/1998 |
| 5808496 | Low current comparator with hysteresis An accurate, low-current integrated circuit comparator includes a differential input stage 10 comprising differential pair transistors 22 and 24, differential pair current mirror transistors 26 and 28, and a constant current source transistor 30. The comp... | 09/15/1998 |
| 5654653 | Reduced system bus receiver setup time by latching unamplified bus voltage An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference vol... | 08/05/1997 |
| 5546035 | Latch circuit having a logical operation function A latch circuit with an NAND function comprises a three-input NAND gate circuit, a first transfer gate connected between a first input terminal and a first input of the NAND gate circuit, a second transfer gate connected between a second input terminal an... | 08/13/1996 |
| 5500614 | Semiconductor memory device A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable acce... | 03/19/1996 |
| 5247208 | Substrate bias generating device and operating method thereof A substrate bias generating circuit including waveform shaping circuits for producing two signals having different phases on the basis of signals in phase extracted from a ring oscillator and two logic gates using these two signals having large phase diff... | 09/21/1993 |
| 4943740 | Ultra fast logic The logic has an extremely high speed, very low number of components and large common mode rejection, and is intended to eliminate the emitter-coupled logic (ECL). The supply voltage and power consumption are small. The logic is particularly for digital s... | 07/24/1990 |
| 4922372 | Solid state overcurrent protection system for circuit breakers Apparatus for detecting a primary fault current in a three-phase current system and converting the detected fault current in the mechanical action for breaking a circuit in which the primary fault current occurred includes a combination of transformers an... | 05/01/1990 |
| 4868904 | Complementary noise-immune logic Logic gates with large logic swings and large noise margins use complementary pull-up and pull-down enhancement-mode drivers. Connected between the input node of the logic gate and the control electrode of each of the drivers is a series combination of a ... | 09/19/1989 |
| 4851711 | Asymmetrical clock chopper delay circuit An asymmetrical delay generator for use in a clock chopping circuit is disclosed. The circuit has a complementary transistor switch memory cell in it. That cell is operated in a mode where one half of the cell operates in saturation mode. That half of the... | 07/25/1989 |
| 4668879 | Dotted "or" function for current controlled gates A "dotted or" logic circuit comprising Current Controlled Gate (CCG) circuits is described. In accordance with the present invention, Schottky diodes are cross-coupled between the dotted CCG circuits. Specifically, a Schottky diode is connected between th... | 05/26/1987 |
| 4613767 | Low forward-voltage drop SCR An SCR having a reduced forward-voltage drop comprising an independently powered latch circuit driving an output transistor in combination with an additional turn-off transistor. The SCR provides saturated operation of the output transistor and self-commu... | 09/23/1986 |
| 4599526 | Clocked latching circuit A digital latching circuit includes a quantizer having an input pair of emitter-coupled transistors connected with output transimpedance circuits. The quantizer is responsive to the state of an input signal applied to the input pair for producing from the... | 07/08/1986 |
| 4580244 | Bipolar memory cell A monolithically integrated memory cell having an improved clamped diode load is provided for improving write pulse width and write recovery times. A pair of latchable cross-coupled multi-emitter NPN transistors have a first emitter connected to a stand-b... | 04/01/1986 |
