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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 8179178 | Registers with reduced voltage clocks A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage lev... | 05/15/2012 |
| 8106698 | Pulse-based flip-flop having scan input signal A flip-flop for transmitting a scan input and data for scan-testing a semiconductor circuit is provided. The flip-flop includes a first pulse signal generator which generates a first pulse signal in response to a scan enable signal and an inversed scan input signal.... | 01/31/2012 |
| 8026754 | Low latency flop circuit A flop circuit comprises a precharge circuit for precharging a first node in response to an occurrence of a first phase of a timing signal, and a discharge circuit for conditionally discharging the first node in response to an occurrence of a second phase of the tim... | 09/27/2011 |
| 7994836 | Latch with clocked devices A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a sec... | 08/09/2011 |
| 7973581 | Phase detector, phase comparator, and clock synchronizing device A flip-flop circuit includes: a first latch circuit that receives input of a data signal and a rise delay clock signal, raises a signal of a first node according to the fall of the rise delay clock signal, and lowers the signal of the first node according to the ris... | 07/05/2011 |
| 7961024 | Low power pulse-triggered flip-flop A low power pulse-triggered flip-flop comprises a latch containing a first conductive line and a first connection point and a pulse generator linking to the latch. The pulse generator includes a first N-transistor, a second N-transistor, a third N-transistor, a firs... | 06/14/2011 |
| 7956662 | Flip-flop circuit with internal level shifter A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received ... | 06/07/2011 |
| 7884658 | Circuits for forming the inputs of a latch Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common m... | 02/08/2011 |
| 7863959 | Apparatus and methods for a high-voltage latch Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second trans... | 01/04/2011 |
| 7830190 | Data latch circuit with a phase selector The present invention provides a data latch circuit. The data latch circuit includes a first data latch unit, a second data latch unit, a third data latch unit, and a phase selector. The first data latch unit is used for latching a first input data according to a fi... | 11/09/2010 |
| 7804346 | Level converting flip-flop and method of operating the same A level converting flip-flop may include a data input circuit, a clocking circuit, a current mirror circuit, and/or a latch circuit. The data input circuit may be configured to generate a pull-up current in response to an input data signal having one of an input sup... | 09/28/2010 |
| 7791389 | State retaining power gated latch and method therefor A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch an... | 09/07/2010 |
| 7782107 | Method and apparatus for an event tolerant storage circuit An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing... | 08/24/2010 |
| 7764102 | Pulse-generator circuit and circuit arrangement Pulse-generator circuit for generating an input signal for a flip-flop circuit from a clock-pulse signal and a data signal. The circuit includes a control unit for controlling a clock-pulse field effect transistor, a logic field effect transistor and a feedback fiel... | 07/27/2010 |
| 7714628 | Soft error robust flip-flops A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the tra... | 05/11/2010 |
| 7622977 | Ramped clock digital storage control Disclosed herein are digital systems and methods for use with a ramped clock signal. The digital system includes an input element having a data input to receive a data signal, a control input to receive a control signal, and a dynamic node to be driven by the ramped... | 11/24/2009 |
| 7525361 | High speed flip-flops and complex gates using the same In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and ... | 04/28/2009 |
| 7525362 | Circuit for and method of preventing an error in a flip-flop A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with each of the input data and redundant data at predetermined nodes of the ... | 04/28/2009 |
| 7440534 | Master-slave flip-flop, trigger flip-flop and counter A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-sl... | 10/21/2008 |
| 7437800 | Clock gating circuit Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises provid... | 10/21/2008 |
| 7425855 | Set/reset latch with minimum single event upset A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in... | 09/16/2008 |
| 7420402 | Flip-flops, shift registers, and active-matrix display devices A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics ... | 09/02/2008 |
| 7405606 | D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele... | 07/29/2008 |
| 7405605 | Storage elements using nanotube switching elements Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, ma... | 07/29/2008 |
| 7388416 | Latch circuit, 4-phase clock generator, and receiving circuit A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data reading unit reads both a first input data and a second input data, a... | 06/17/2008 |
| 7388420 | Rewriteable electronic fuses Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predet... | 06/17/2008 |
| 7378890 | Programmable low-power high-frequency divider Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also describ... | 05/27/2008 |
| 7365596 | State retention within a data processing system Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when ... | 04/29/2008 |
| 7345519 | Flip-flop circuit A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that is shorter than the clock cycle, wherein only three N-type transistors... | 03/18/2008 |
| 7342429 | Programmable low-power high-frequency divider Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also describ... | 03/11/2008 |
| 7332780 | Inverter, semiconductor logic circuit, static random access memory and data latch circuit A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type ... | 02/19/2008 |
| 7327628 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 02/05/2008 |
| 7327163 | Voltage translator having minimized power dissipation A voltage translator circuit for low level to high level voltage translation includes a plurality of transistors coupled to an inverter for receiving a common input signal at an input node of the plurality of transistors and passing a translated output signal to the... | 02/05/2008 |
| 7327629 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 02/05/2008 |
| 7323920 | Soft-error rate improvement in a latch using low-pass filtering In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass f... | 01/29/2008 |
| 7324796 | Low temperature co-fired ceramic sub-harmonic mixer A sub harmonic mixer has improved electrical performance in a small package size. The mixer has a low temperature co-fired ceramic substrate. Coupled lines are located within the substrate and connected to an LO port, an RF port and an intermediate frequency port. T... | 01/29/2008 |
| 7319344 | Pulsed flop with embedded logic In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of th... | 01/15/2008 |
| 7319353 | Non-latching enveloping curves generator An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steer... | 01/15/2008 |
| 7301382 | Data latch circuit and electronic device The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the othe... | 11/27/2007 |
| 7301373 | Asymmetric precharged flip flop A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Dep... | 11/27/2007 |
