Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 8143929 | Flip-flop having shared feedback and method of operation A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a t... | 03/27/2012 |
| 8120404 | Flip-flop circuit with internal level shifter A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received ... | 02/21/2012 |
| 8115531 | D flip-flop having enhanced immunity to single-event upsets and method of operation thereof A D flip-flop (DFF), a method of operating a DFF, a latch and a library of standard logic elements including standard logic elements corresponding to a DFF and a latch. In one embodiment, the DFF has a data input and a data output and includes: (1) a master stage pa... | 02/14/2012 |
| 8085076 | Data retention flip flop for low power applications A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master ci... | 12/27/2011 |
| 8076965 | Low leakage data retention flip flop A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circ... | 12/13/2011 |
| 8026752 | Delay circuit Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an i... | 09/27/2011 |
| 8008959 | Flip-flop circuit that latches inputted data A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pai... | 08/30/2011 |
| 7982514 | State-retentive master-slave flip flop to reduce standby leakage current A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and s... | 07/19/2011 |
| 7872512 | Robust time borrowing pulse latches Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled... | 01/18/2011 |
| 7868677 | Low power flip-flop circuit A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal a... | 01/11/2011 |
| 7843243 | Flip-flop circuit, pipeline circuit including a flip-flop circuit, and method of operating a flip-flop circuit Example embodiments relate to an electronic circuit, for example, a flip-flop circuit, a pipeline circuit including the flip-flop circuit and a method for operating the flip-flop circuit. A flip-flop circuit may include a precharge transistor configured to precharge... | 11/30/2010 |
| 7843244 | Low latency synchronizer circuit A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input ... | 11/30/2010 |
| 7772905 | Semiconductor integrated circuit apparatus It is made possible to provide a flip-flop circuit capable of implementing the error correction function with a small area increase as far as possible and a pipeline system using such a flip-flop circuit. A flip-flop circuit includes: a flip-flop configured to opera... | 08/10/2010 |
| 7768331 | State-retentive master-slave flip flop to reduce standby leakage current A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and s... | 08/03/2010 |
| 7750706 | Circuits, architectures, apparatuses, systems, and methods for low voltage clock delay generation Circuits, systems, and methods for generating a delayed clock signal. The circuit generally includes a first ramp generator configured to produce a first ramp signal in response to a reference clock signal, a first comparison circuit configured to compare the first ... | 07/06/2010 |
| 7649395 | Scan flip-flop with internal latency for scan input A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The ... | 01/19/2010 |
| 7639056 | Ultra low area overhead retention flip-flop for power-down applications In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a f... | 12/29/2009 |
| 7626434 | Low leakage state retention circuit In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive th... | 12/01/2009 |
| 7622975 | Circuit having a local power block for leakage reduction A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portio... | 11/24/2009 |
| 7616040 | Flip-flop and semiconductor integrated circuit A flip-flop is disclosed which includes: a clock supply circuit configured to output or fix a clock signal alternating between two predetermined states in accordance with a sleep signal; a first holding circuit configured to fetch or hold an input signal in accordan... | 11/10/2009 |
| 7616041 | Data retention in operational and sleep modes A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output ... | 11/10/2009 |
| 7583121 | Flip-flop having logic state retention during a power down mode and method therefor A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for... | 09/01/2009 |
| 7576582 | Low-power clock gating circuit Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage curre... | 08/18/2009 |
| 7560964 | Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility An edge triggered system is provided having a data and scan input includes a latch device having a clock input and an AND gate, coupled to the latch device, structured and arranged to receive a first clock signal and an inverted clock signal to generate a clock to t... | 07/14/2009 |
| 7560965 | Scannable flip-flop with non-volatile storage element and method A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a pred... | 07/14/2009 |
| 7560966 | Method of testing connectivity using dual operational mode CML latch A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at le... | 07/14/2009 |
| 7548102 | Data latch with minimal setup time and launch delay The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second contro... | 06/16/2009 |
| 7514975 | Data retention in operational and sleep modes A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output ... | 04/07/2009 |
| 7495492 | Dynamic latch state saving device and protocol The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated... | 02/24/2009 |
| 7492201 | Two-latch clocked-LSSD flip-flop A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches. ... | 02/17/2009 |
| 7482851 | Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility An edge triggered system is provided having a data and scan input includes a latch device having a clock input and an AND gate, coupled to the latch device, structured and arranged to receive a first clock signal and an inverted clock signal to generate a clock to t... | 01/27/2009 |
| 7440534 | Master-slave flip-flop, trigger flip-flop and counter A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-sl... | 10/21/2008 |
| 7437634 | Test scan cells A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan flip-flop defining a scan test circuit. Such a scan test circuit is coupled... | 10/14/2008 |
| 7427875 | Flip-flop circuit Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or... | 09/23/2008 |
| 7425855 | Set/reset latch with minimum single event upset A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in... | 09/16/2008 |
| 7420403 | Latch circuit and flip-flop A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit is presented that uses both low and high threshold inverters. The multi-threshold latch circuit includes: a low threshold forward clock inverter inverting an input-termi... | 09/02/2008 |
| 7420402 | Flip-flops, shift registers, and active-matrix display devices A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics ... | 09/02/2008 |
| 7411432 | Integrated circuits and complementary CMOS circuits for frequency dividers An integrated circuit of an embodiment may comprise synchronous logic, combinational logic, and clock circuitry to clock the synchronous logic through various states dependent on the combinational logic. The synchronous logic may comprise a plurality of master-slave... | 08/12/2008 |
| 7408393 | Master-slave flip-flop and clocking scheme A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its c... | 08/05/2008 |
| 7405606 | D flip-flop A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback ele... | 07/29/2008 |
