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| Number | Title | Issue Date |
| 8040156 | Lock detection circuit and lock detecting method Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection ... | 10/18/2011 |
| 7924061 | Apparatus for detecting clock failure and method therefor A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. T... | 04/12/2011 |
| 7855581 | Real time clock monitoring method and system Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short ... | 12/21/2010 |
| 7768318 | Detection of a disturbance in the state of an electronic circuit flip-flop A method and a circuit for detecting a disturbance of a state of at least one first flip-flop from a group of several first flip-flops of an electronic circuit, wherein: the respective outputs of the first flip-flops in the group are, independently from their functi... | 08/03/2010 |
| 7710161 | Digital low frequency detector A digital circuit is disclosed for detecting clock activity in an integrated circuit (IC) device. In one implementation, a clock detection circuit can include two flip flops. A first flip flop detects activity on the clock being tested (e.g., the flip flop is set wh... | 05/04/2010 |
| 7622961 | Method and apparatus for late timing transition detection Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are de... | 11/24/2009 |
| 7498848 | System and method for monitoring clock signal in an integrated circuit A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circui... | 03/03/2009 |
| 7486114 | Signal detector with calibration circuit arrangement A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and referen... | 02/03/2009 |
| 7414438 | Clock based voltage deviation detector The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail... | 08/19/2008 |
| 7391240 | Clock anomaly detection circuit and clock anomaly detection method A clock anomaly detection circuit includes: a dividing unit configured to output a divided target clock by dividing frequency of a target clock; a first time width measurement unit configured to obtain values of the divided target clock using rising edges of a monit... | 06/24/2008 |
| 7353412 | Electrical circuit for controlling power supply and motor vehicle built-in device being operably connected to an external power supply The number of electrical devices implemented in motor vehicles and supplied with electricity by the motor vehicle battery rises with each generation. The manufacturers of motor vehicles make great demands on electrical device to be built-in their motor vehicles, esp... | 04/01/2008 |
| 7321244 | Clock switching device and clock switching method A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current cloc... | 01/22/2008 |
| 7302362 | System and method for efficient and collective adjustment of sensor reporting ranges for long-lived queries A system and method for providing energy-efficient support of continuous aggregate queries in a sensor network by efficiently orchestrating the collection and transmission of data gathered by a collective set of sensors to ensure conformance to a specified QoI bound... | 11/27/2007 |
| 7297922 | Optical receiver protection circuit An apparatus for optical receiver circuit protection includes a bias source, a bias monitor, and a comparator. The bias source is to provide a bias voltage to an optical receiver. The bias monitor is coupled to measure a current through the optical receiver, where t... | 11/20/2007 |
| 7296170 | Clock controller with clock source fail-safe logic A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast in... | 11/13/2007 |
| 7279950 | Method and system for high frequency clock signal gating A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled p... | 10/09/2007 |
| 7276955 | Circuit and method for stable fuse detection A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and ... | 10/02/2007 |
| 7265590 | Semiconductor apparatus for monitoring critical path delay characteristics of a target circuit A semiconductor apparatus for flexibly and effectively configuring a delay monitor circuit without an increase in circuit scale includes a delay signal generation circuit for switching the configuration of delay element arrays based on first configuration informatio... | 09/04/2007 |
| 7257323 | Signal-off detection circuit and optical receiving device using the same This invention offers a signal-off detection circuit allowing arbitrary setting of an issuing time (response time) of a signal disconnection alarm without being affected by a time constant of a direct current feedback circuit giving an offset voltage to an amplifier... | 08/14/2007 |
| 7242223 | Clock frequency monitor A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given ... | 07/10/2007 |
| 7227387 | Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs... | 06/05/2007 |
| 7215210 | Clock signal outputting method, clock shaper and electronic equipment using the clock shaper A clock signal outputting method in which either a clock signal based on a signal from the outside or an alternative clock signal from a fixed oscillator is selected and outputted, wherein, when the clock signal is selected to be outputted, the fixed oscillator is p... | 05/08/2007 |
| 7211875 | Voltage-controlled capacitive element and semiconductor integrated circuit An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+ diffusion regions are placed in two areas in the surface of ... | 05/01/2007 |
| 7200186 | Methods and apparatus for reducing power usage of a transmitter and receiver coupled via a differential serial data link Methods and apparatus are disclosed for using in-band signal(s) over a differential serial data link to reduce power usage of a transmitter and receiver coupled by the link. ... | 04/03/2007 |
| 7183831 | Clock switching circuit A clock switching circuit suitably adapted to stable switching operation of high-frequency multiphase clock signals. The clock switching circuit receives two clock signals and selectively outputs one of the two clock signals in accordance with a selection signal. Th... | 02/27/2007 |
| 7180345 | Apparatus and a method to provide time-based edge-rate compensation A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a... | 02/20/2007 |
| 7176708 | Receiver circuit In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predet... | 02/13/2007 |
| 7173495 | Redundant back-up PLL oscillator phase-locked to primary oscillator with fail-over to back-up oscillator without a third oscillator A redundant-source clock generator has only two oscillators, rather than three oscillators. A secondary oscillator is phase-locked to a primary clock from a primary oscillator using a phase detector, charge pump, and filter that generate a control voltage to the sec... | 02/06/2007 |
| 7170949 | Methods and apparatus for signaling on a differential link Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link. ... | 01/30/2007 |
| 7155628 | Integrated circuit and method for detecting the state of an oscillating signal Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal ... | 12/26/2006 |
| 7155603 | Circuit arrangement for detecting the state of at least one electrical switch Circuit arrangement for detecting the state of at least one electrical switch having at least one set input (Set1, Set2, Set3) in each case and at least one sensor output (Sensor1, Sensor2, Sensor3) in each case, each of whi... | 12/26/2006 |
| 7136429 | Passive redundant digital data receiver with dual comparator edge detection A passive coupling structure constructed using printed circuit board traces is used to separate the low and high frequency components of an incoming digital signal. The low and high frequency components of the signal are sent to separate receivers on an integrated c... | 11/14/2006 |
| 7130340 | Noise margin self-diagnostic receiver logic A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a high reference voltage, a second comparator for comparing the signal voltage to a low reference voltage, and... | 10/31/2006 |
| 7129800 | Compensation technique to mitigate aging effects in integrated circuit components A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the... | 10/31/2006 |
| 7126371 | Multi-function IC card When a reset signal /RESET is “L”, a flip-flop circuit holds “1”; on the other hand, a flip-flop circuit holds “0”. When the reset signal /RESET becomes “H”, the flip-flop circuits captures data in synchronous with a clock signal. When a power supply... | 10/24/2006 |
| 7113003 | Presence indication signal associated with an attachment According to some embodiments, a presence indication associated with an attachment is provided. ... | 09/26/2006 |
| 7106116 | Pulse duty deterioration detection circuit A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitor... | 09/12/2006 |
| 7102392 | Signal detector for high-speed serdes An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications ... | 09/05/2006 |
| 7081840 | Decoder for decoding symmetric/asymmetric delay modulation signal and the method thereof The invention relates to a decoder for decoding a received signal to obtain a corresponding decoded bit series. The signal comprises a plurality of pulses. The decoder comprises a memory, a counting module, a transform module, and a logic module. The memory is for s... | 07/25/2006 |
| 7068734 | Passive redundant digital data receiver with schmitt-trigger A passive coupling structure constructed using printed circuit board traces is used to separate the low and high frequency components of an incoming digital signal. The low and high frequency components of the signal are sent to separate receivers on an integrated c... | 06/27/2006 |
