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| Number | Title | Issue Date |
| 7919991 | Comparator circuit A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power th... | 04/05/2011 |
| 7795924 | Phase detecting module and detecting method thereof A phase detecting module capable of optimizing detection accuracy and noise robustness, and a detecting method, are included. The phase detecting module includes a phase detecting circuit, an energy estimating circuit and a selecting circuit. The phase detecting cir... | 09/14/2010 |
| 7791377 | Hierarchical time to digital converter A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of ... | 09/07/2010 |
| 7777527 | Phase detection apparatus There is provided a phase detection apparatus that can accurately detect a phase difference between an input signal and a reference signal even when the input signal and the reference signal have different duty cycles. A phase detection apparatus according to an asp... | 08/17/2010 |
| 7609092 | Automatic phase-detection circuit for clocks with known ratios An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the othe... | 10/27/2009 |
| 7443251 | Digital phase and frequency detector Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a p... | 10/28/2008 |
| 7425851 | Phase-locked loop with incremental phase detectors and a converter for combining a logical operation with a digital to analog conversion The invention relates to a phase-locked loop comprising a voltage controlled oscillator and having a frequency control input for controlling the frequency of the output signal. The phase-locked loop also has a phase comparator for deriving a control signal from a ph... | 09/16/2008 |
| 7411426 | Phase detector for RZ A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the ... | 08/12/2008 |
| 7400204 | Linear phase detector and charge pump A phase detector detects a phase difference between a first and second signal received by a phase detector. A charge is supplied by a charge pump circuit that corresponds to the phase difference using a phase difference to charge conversion that is substantially lin... | 07/15/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7340219 | Method and system for multisite RF transceiver testing According to one embodiment of the invention, a system for testing electronic devices includes a first RF source operable to output a first signal, a second RF source operable to output a second signal, a combiner coupled to the first and second RF sources and opera... | 03/04/2008 |
| 7336106 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 02/26/2008 |
| 7337083 | Process for identification of the direction of rotation of two periodic electrical signals at the same frequency A process and apparatus for identification of the direction of rotation of two periodic electrical signals present on two electrical conductors, particularly of a three-phase power system. In this process, the signals are sampled from two conductors by two wires of ... | 02/26/2008 |
| 7336112 | False lock protection in a delay-locked loop (DLL) A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicat... | 02/26/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7313211 | Method and apparatus for phase detection The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllab... | 12/25/2007 |
| 7310397 | Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock p... | 12/18/2007 |
| 7304517 | Duty cycle corrector A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circui... | 12/04/2007 |
| 7292179 | Instantaneous passive range finding A method and apparatus for use in determining the range in a single time sample from a platform to a target are disclosed. The method includes receiving radiation emanating from the target at two points on the platform in a common time sample; detecting the received... | 11/06/2007 |
| 7286625 | High-speed clock and data recovery circuit A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.1... | 10/23/2007 |
| 7271622 | Quadrature voltage controlled oscillators with phase shift detector In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows... | 09/18/2007 |
| 7263151 | High frequency loss of signal detector Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data wi... | 08/28/2007 |
| 7248086 | Leakage compensation for capacitors in loop filters A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be ... | 07/24/2007 |
| 7245685 | Filtering for timing distribution system in networking products A timing distribution apparatus. The apparatus includes a source for producing a signal. The apparatus includes a first filter for removing jitter from the signal. The apparatus includes a second filter for removing wander from the signal separate and apart from the... | 07/17/2007 |
| 7227919 | Data sampler for digital frequency/phase determination A digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an... | 06/05/2007 |
| 7203259 | Phase interpolator An arrangement for generating a clock signal. Embodiments provide a method, apparatus, system, and machine-readable medium to interpolate phases of a reference clock signal to output an interpolated clock signal. Some embodiments may output the clock signal as a rec... | 04/10/2007 |
| 7202707 | High frequency binary phase detector A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock signal at a second frequency. The frequency of the first clock signal is a multiple of the frequency of t... | 04/10/2007 |
| 7197102 | Method and apparatus for clock-and-data recovery using a secondary delay-locked loop A clock and data recovery circuit includes a delay-locked-loop adapted to recover data from a data stream: and a phase-locked-loop in communication with the delay-locked-loop and adapted to recover a clock signal from the data stream. ... | 03/27/2007 |
| 7195728 | Method for molding rubber product A method of molding a rubber product from a rubber compound by a molding apparatus having a kneading region. A full amount of carbon black (CB) and a full amount of process oil, together with other auxiliary materials except vulcanizing chemicals, are compounded wit... | 03/27/2007 |
| 7183810 | Circuit and method for detecting phase A circuit for detecting phase includes a first inverter, a second inverter, a differential amplifier, an output load latch and an output latch. The first and second inverters receive an input signal and an inverted input signal to generate first and second different... | 02/27/2007 |
| 7173462 | Second order delay-locked loop for data recovery A DLL system includes a phase detector coupled to an input signal for generating a first phase error signal according to the input signal and a clock signal; an up-down counter coupled to the phase detector for generating a counting signal according to the first pha... | 02/06/2007 |
| 7170323 | Delay locked loop harmonic detector and associated method We describe and claim a delay locked loop harmonic detector and associated method. A delay locked loop includes a detection circuit to generate a detection signal responsive to an input clock and a control circuit to synchronize the delay locked loop to a fundamenta... | 01/30/2007 |
| 7167031 | Synchronizing circuit provided with hysteresis phase comparator A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further incl... | 01/23/2007 |
| 7129794 | Phase detector for reducing noise The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the dete... | 10/31/2006 |
| 7119583 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 10/10/2006 |
| 7109806 | Device and method for detecting phase difference and PLL using the same A phase detector includes a first control unit and a second control unit to generate a first control pulse and a second control pulse representative of a phase difference between a reference signal and a first clock signal. The first control unit receives the refere... | 09/19/2006 |
| 7109760 | Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles Delay-locked loop (DLL) integrated circuits include digital phase comparators that are unaffected by variable duty cycle ratios. These phase comparators determine a shortest direction to phase lock before establishing a value of a compare signal (COMP) that specifie... | 09/19/2006 |
| 7103131 | System and method for half-rate clock phase detection A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q1; latching the divided data with a second half-rate clock... | 09/05/2006 |
| 7088796 | Phase detector customized for clock synthesis unit A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic... | 08/08/2006 |
| 7087890 | Rotating-body control device A P-ECU controls an actuator which drives a shift control mechanism. An encoder signal acquisition unit acquires signals output from an encoder which detects a rotational angle of the actuator. A counter calculates a count value from the output signals of the encode... | 08/08/2006 |
