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| Number | Title | Issue Date |
| 7362159 | Semiconductor integrated circuit There is here disclosed a semiconductor integrated circuit comprising a laser beam irradiation object having one end portion at which a first potential is applied, a first transistor has a source and a drain wherein one of the source and the drain to which the other... | 04/22/2008 |
| 7358715 | Semiconductor integrated circuit By mounting, on a semiconductor integrated circuit, a clock stability waiting circuit 4 for deciding whether a clock signal generated by a high speed clock generating circuit 2 is stable or not, a scan pass control circuit 7 capable of switching... | 04/15/2008 |
| 7355534 | Serial-to-parallel conversion circuit, and semiconductor display device employing the same In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency ... | 04/08/2008 |
| 7342429 | Programmable low-power high-frequency divider Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also describ... | 03/11/2008 |
| 7319353 | Non-latching enveloping curves generator An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steer... | 01/15/2008 |
| 7304518 | Track and hold circuit A track and hold circuit (1) comprising:—a linear amplifier (2) receiving a differential analog signal (D+, D−) and being controlled by a first binary clock signal (H+) having a first phase,—the linear amplifier (2) providing a feed-forwar... | 12/04/2007 |
| 7285999 | Circuit for use in frequency or phase detector A tracking data cell (10) comprising: —a pair of track and hold circuits (1, 1′) coupled to a first multiplexer (5), —a clock signal (H+, H−) being inputted substantially in anti-phase in the respective track and hold circuits (1, 1 | 10/23/2007 |
| 7287171 | Systems and methods for reducing static and total power consumption in programmable logic device architectures A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the synthesis, placement, routing, ... | 10/23/2007 |
| 7218160 | Semiconductor integrated circuit A semiconductor integrated circuit according to the present invention comprises a latch circuit, a retaining circuit, and a feedback circuit, wherein the latch circuit inputs therein an input data signal, a clock signal and a feedback signal and outputs an output da... | 05/15/2007 |
| 7180973 | Programmable low-power high-frequency divider A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to ... | 02/20/2007 |
| 7161405 | Level shift circuit A level shift circuit includes first and second inverters and an inversion circuit. The first inverter has a first input terminal and a first output terminal for generating the output signal. The first inverter includes a first transistor having a first current driv... | 01/09/2007 |
| 7138850 | High-gain synchronizer circuitry and methods High-gain synchronizer circuitry and methods are provided that reduce the meta-stable resolve time of a synchronizer circuit. The high-gain synchronizer is made up of high-gain latch circuits. The high-gain latch circuits are made up of a series of inverters that at... | 11/21/2006 |
| 7106116 | Pulse duty deterioration detection circuit A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitor... | 09/12/2006 |
| 7102418 | Method and apparatus for producing a reference voltage The invention relates to a method and an apparatus for producing a reference voltage that is applied to reference voltage inputs on receiver units in order to discriminate between the logic states of a data signal that is transmitted to a receiver end. A transmissio... | 09/05/2006 |
| 7075350 | Programmable low-power high-frequency divider A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to ... | 07/11/2006 |
| 7068076 | Semiconductor device and display device A circuit capable of reducing a consumption current is provided for a digital display device composed of unipolar TFTs. There is provided a latch circuit for holding a digital video signal. According to the latch circuit, when the digital video signal is inputted to... | 06/27/2006 |
| 7068088 | Soft-error rate improvement in a latch In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. The input of a first inverter is connected to the output of a second inverter. The input of a second inverter is connected to the output of the first in... | 06/27/2006 |
| 7061275 | Field programmable gate array A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that ca... | 06/13/2006 |
| 7038485 | Terminating resistor device and a method for testing a terminating resistor circuit An object of the present invention is to provide a terminating resistor device and a testing method, by which the resistance value of a terminating resistor circuit can be test effectively. The test procedure starts with setting a MUXSCANFF circuit which functions a... | 05/02/2006 |
| 7003049 | Fractional-N digital modulation with analog IQ interface Digital I and Q (NRZ) data streams are generated by specially configured conversion circuits, the outputs of which are applied to a F-N synthesizer to modulate the synthesizer. All illustrative conversion circuit employs a system of comparators to detect the state o... | 02/21/2006 |
| 6917236 | Method and apparatus for level shifting A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS tec... | 07/12/2005 |
| 6794915 | MOS latch with three stable operating points A tristable latch circuit fabricated utilizing standard MOS process technology includes a biasing element for identically biasing the MOS transistors in triode (as opposed to saturation) to implement a third stable operating point. ... | 09/21/2004 |
| 6765433 | Low power implementation for input signals of integrated circuits Integrated circuit device that uses tristate switching means to disconnect input/output pins from input buffers during a power down mode, thereby preventing current leakage through partially turned on MOS transistors inside input buffers. A transition detection mean... | 07/20/2004 |
| 6731151 | Method and apparatus for level shifting A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS tec... | 05/04/2004 |
| 6727684 | Magnetic field sensor A magnetic field sensor includes: a Hall element; a voltage amplifier for amplifying an output voltage from the Hall element so as to output an amplified signal; a voltage comparison circuit for receiving the amplified signal; a switch circuit provided between the v... | 04/27/2004 |
| 6633503 | Voltage differential sensing circuit and methods of using same A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by ... | 10/14/2003 |
| 6538485 | Dual tristate path output buffer control An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) co... | 03/25/2003 |
| 6529033 | Area efficient clock inverting circuit for design for testability A method for fabricating IC devices including both rising edge-triggered circuits (e.g., flip-flops or latches) and falling edge-triggered circuits in which a clock signal line is selectively inverted by an on-chip clock signal inverting circuit and appli... | 03/04/2003 |
| 6509764 | Low component circuit for reducing power dissipation capacitance An improved pre-driver circuit 33, which uses only three additional components to bypass the back-gate current blocking diodes for increased circuit speed during normal operation, while reducing the Ioff current and satisfying over-voltage tole... | 01/21/2003 |
| 6310491 | Sequential logic circuit with active and sleep modes A sequential logic circuit having active and sleep modes prevents stored information from being lost immediately after the transition from a sleep mode to an active mode. This sequential logic circuit includes a latch circuit having an input terminal to w... | 10/30/2001 |
| 6249148 | Low power variable base drive circuit A variable base drive output circuit that is operational for low-potential power supplies. The output circuit includes a current regulating branch and a base drive branch. A control transistor is logically coupled to an enable signal and an input signal t... | 06/19/2001 |
| 6166561 | Method and apparatus for protecting off chip driver circuitry employing a split rail power supply OCD circuitry is provided for an integrated circuit having a split rail power supply providing a first and a second voltage. The OCD circuitry comprises a tristate logic circuit adapted to control the OCD and a detection circuit coupled to the tristate lo... | 12/26/2000 |
| 6154077 | Bistable flip-flop In a known bitable flip-flop, a first inverter stage (1) is driven by an input signal (D), a second inverter stage (2) by a clock signal (CLK), and a third inverter stage (3) by an output signal (INV2) of the second inverter stage (2). In order to buffer ... | 11/28/2000 |
| 6047221 | Method for steady-state identification based upon identified dynamics A method for modeling a steady-state network in the absence of steady-state historical data. A steady-state neural network can be tied by impressing the dynamics of the system onto the input data during the training operation by first determining the dyna... | 04/04/2000 |
| 6031390 | Asynchronous registers with embedded acknowledge collection An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value a... | 02/29/2000 |
| 5969554 | Multi-function pre-driver circuit with slew rate control, tri-state operation, and level-shifting A pre-driver circuit in an I/O circuit for an integrated circuit performs the combined functions of voltage level shifting, slew rate control, and tri-state capability, in a single circuit to avoid additional delay caused by implementing any combination o... | 10/19/1999 |
| 5815019 | Flip-flop circuit operating on low voltage Disclosed herein is a flip/flop circuit of a master-slave type including master side and slave side latch/hold circuits 1 and 2 each being of an ECL vertical 1-step construction, first and second bias circuits 3 and 4 for biasing current sources Tr's 21 t... | 09/29/1998 |
| 5760634 | High speed, low noise output buffer An output buffer device utilizes a PMOS transistor as a first pull-up element and an NMOS transistor as a second pull-up element. An output signal is used to control a feedback circuit. An output signal is switched from a low to high voltage by a trigger ... | 06/02/1998 |
| 5656959 | Clock synthesizer dual function pin system and method therefor An improved clock synthesizer system and method therefor is described which uses a plurality of dual function pins to apply a frequency selection code while in a first operating mode and to transmit buffered clock signal while in a second operating mode t... | 08/12/1997 |
| 5644259 | Reset circuit and integrated circuit including the same A reset circuit includes a plurality of registers (R1-R8) in which a logical value at power on is shifted and set to a predetermined logical value after a predetermined time has elapsed since a power supply was switched on and a logic circuit (1) for outp... | 07/01/1997 |
