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| Number | Title | Issue Date |
| 8022743 | Pulse width modulation circuit and liquid jet printing apparatus A pulse width modulation circuit includes: a reference signal generator which generates a plurality of mutually differing reference signals; a comparator which compares the reference signals and an input signal with respect to magnitude, and outputs results of the c... | 09/20/2011 |
| 8018263 | Pulse generating circuit and pulse width modulator A pulse generating unit receives a clock at a predetermined frequency, and generates a pulse signal which transits synchronously with the positive edge of the clock. A flip-flop acquires the pulse signal every time a positive edge occurs in an inverted clock output ... | 09/13/2011 |
| 7928786 | Clock buffer circuit of semiconductor device configured to generate an internal clock signal A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase cl... | 04/19/2011 |
| 7872510 | Duty cycle correction circuit of semiconductor memory apparatus A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock si... | 01/18/2011 |
| 7710175 | Pulse width modulation circuit and switching amplifier using the same A pulse width modulation circuit includes a first electric-charge accumulator; a second electric-charge accumulator; a first current generator which generates a first current corresponding to the amplitude of an input AC voltage; a second current generator which gen... | 05/04/2010 |
| 7701275 | Time-limiting protection and control circuit for protecting an element by limiting a pulse width of an input pulse A time limiter protects a light emitting diode coupled to an output of a current driver by preventing the light emitting diode from working overtime under a high current and from being overheated and burnt down, no matter whether a pulse width of an input pulse is l... | 04/20/2010 |
| 7456668 | Pulse width modulation circuit and switching amplifier using the same A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C1 during the first period T1 of the clock signal MCLK based on a current based on an audio signal eS, changes the voltage of the firs... | 11/25/2008 |
| 7436235 | Digital clock modulator A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A m... | 10/14/2008 |
| 7430140 | Method and device for improved data valid window in response to temperature variation A memory architecture and a method of operating the same can provide a substantially constant data valid window (DVW) irrespective of a temperature for the memory device. Generally, a memory device can receive an access request, determine a temperature of the memory... | 09/30/2008 |
| 7423466 | Apparatus for enabling duty cycle locking at the rising/falling edge of the clock An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating control signals. An address decoder is connected to the counter for gene... | 09/09/2008 |
| 7411435 | Duty detection circuit A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an a... | 08/12/2008 |
| 7397291 | Clock jitter minimization in a continuous time sigma delta analog-to-digital converter A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with a... | 07/08/2008 |
| 7397290 | Method and relative circuit for generating a control voltage of a synchronous rectifier A control voltage for a synchronous rectifying transistor is generated with the desired anticipation time. The anticipation time is continuously controlled with a closed-loop technique by comparing it with the duration of a reference pulse. The resulting error signa... | 07/08/2008 |
| 7378889 | Pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit A pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit is used in a power supply. The present invention comprises a hysteresis comparison circuit extracting a feedback voltage, a high threshold voltage an... | 05/27/2008 |
| 7375563 | Duty cycle correction using input clock and feedback clock of phase-locked-loop (PLL) A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) of the PLL drives a feedback ... | 05/20/2008 |
| 7372327 | Input structure for a power amplifier and associated methods A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to main... | 05/13/2008 |
| 7372312 | Pulse width modulation generating circuit A pulse width modulation (PWM) generating circuit includes a first comparator, a first resistor, a second resistor, a third resistor, a fourth resistor, a capacitor, and a diode. The first resistor and the second resistor are connected in series between a voltage in... | 05/13/2008 |
| 7368966 | Clock generator and clock duty cycle correction method A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a ... | 05/06/2008 |
| 7368963 | Delay locked loop for use in semiconductor memory device and method thereof A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locke... | 05/06/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7362648 | Memory system, memory device, and output data strobe signal generating method An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip... | 04/22/2008 |
| 7358785 | Apparatus and method for extracting a maximum pulse width of a pulse width limiter An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells util... | 04/15/2008 |
| 7352220 | Measuring average of phase voltage of a frequency converter based on an idealized waveform A method and arrangement for determining the effective time of a voltage pulse of phase voltage generated by a frequency converter provided with an intermediate voltage circuit, the voltage pulses of the phase voltage being generated from the upper and lower voltage... | 04/01/2008 |
| 7352224 | Pulse generator and method for generating a pulse train A method for generating a pulse train is provided with adjustable start and end times of individual pulses, in which additional clock signals are generated from a 0th clock signal, the signals which in each case have a frequency of the 0th clock signal and whose pha... | 04/01/2008 |
| 7323919 | Pulse-width modulation circuits of self-oscillation type and pulse-width modulation methods Pulse-width modulation (PWM) circuits and methods integrate a feedback signal and an input signal to generate an integral signal, and generate a PWM signal by switching an output node from a first source voltage to a second source voltage based upon comparing the in... | 01/29/2008 |
| 7321735 | Optical down-converter using universal frequency translation technology A method and system for converting an optical signal to electrical information signals, including demodulated baseband information signals and modulated baseband signals at multiple harmonics. In an embodiment, the optical information signal is amplitude modulated w... | 01/22/2008 |
| 7320049 | Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode ... | 01/15/2008 |
| 7317341 | Duty correction device A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a pulse width of an input clock and output the adjusted clock as an outpu... | 01/08/2008 |
| 7312668 | High resolution PWM generator or digitally controlled oscillator A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal through a series of delays, all of which are controlled by a delay l... | 12/25/2007 |
| 7301417 | Pulse width modulation method and apparatus Disclosed is a pulse width modulation method and apparatus capable of expressing as many values as possible in a pulse width modulation (PWM) period, while maintaining the center of pulse energy substantially equal to the center of the PWM period. For this end, prep... | 11/27/2007 |
| 7295826 | Integrated frequency translation and selectivity with gain control functionality, and applications thereof Methods and apparatuses for frequency selectivity and frequency translation, and applications for such methods and apparatuses, are described herein. The method includes steps of filtering an input signal, and down-converting the filtered input signal. The filtering... | 11/13/2007 |
| 7292835 | Wireless and wired cable modem applications of universal frequency translation technology Frequency translation and applications of same are described herein, including cable modem applications. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and fil... | 11/06/2007 |
| 7282977 | Duty cycle correction device Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first si... | 10/16/2007 |
| 7278069 | Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the chann... | 10/02/2007 |
| 7274240 | Clock control cell A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal ... | 09/25/2007 |
| 7256632 | Pulse width modulation (PWM) controlling module and method for adjusting a PWM signal thereof A pulse width modulation (PWM) controlling module, includes: a PWM controller, a load detector, and an adjusting module. The PWM controller generates a PWM signal that is utilized for controlling a supply voltage applied to an electronic system. The load detector, c... | 08/14/2007 |
| 7250777 | Method and device for measuring resistance A device for measuring a resistance includes a comparator. A D-type flip-flop has its D input connected to the output of the comparator and its latch input connected for receiving a pulse signal at a fixed pulse repetition rate. A reference voltage source is connect... | 07/31/2007 |
| 7246215 | Systolic memory arrays A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank ... | 07/17/2007 |
| 7242233 | Simplified method for limiting clock pulse width The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pu... | 07/10/2007 |
| 7230466 | Data strobe signal generating circuit and data strobe signal generating method Provided is a data strobe signal generating circuit capable of guaranteeing a preamble time (tRPRE). The data strobe signal generating circuit includes: a strobe output driver for outputting a data strobe signal to an outside of a semiconductor device so as to indic... | 06/12/2007 |
