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| Number | Title | Issue Date |
| 8188779 | Duty control buffer circuit and duty correction circuit The circuit includes a duty control buffer and a duty control voltage generator that receives outputs of the duty control buffer, detects a duty error, and generates control signals. The duty control buffer includes a differential stage including unbalanced first an... | 05/29/2012 |
| 8169245 | Duty transition control in pulse width modulation signaling A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process th... | 05/01/2012 |
| 8154331 | Duty correction circuit A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differenti... | 04/10/2012 |
| 8149037 | Clock duty correction circuit A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current s... | 04/03/2012 |
| 8149036 | Semiconductor device A semiconductor device includes a phase division unit, a clock delay unit, a duty cycle correction clock generation unit, and a duty cycle correction voltage generation unit. The phase division unit is configured to divide a phase of a source clock to generate a fir... | 04/03/2012 |
| 8143928 | Duty cycle correction systems and methods Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have fi... | 03/27/2012 |
| 8125259 | Duty cycle distortion (DCD) jitter modeling, calibration and generation methods A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a... | 02/28/2012 |
| 8120402 | PWM control circuit having adjustable minimum duty cycle A pulse width modulated (PWM) controller includes a triangle wave generation circuit generating a triangle wave signal to oscillate between an upper limit voltage and a lower limit voltage. The upper limit voltage and the lower limit voltage are adjustable in respon... | 02/21/2012 |
| 8120403 | Duty detection circuit A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle l... | 02/21/2012 |
| 8106697 | Circuit and method for providing a corrected duty cycle A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal c... | 01/31/2012 |
| 8106695 | Semiconductor device A semiconductor device which has a duty detection circuit that detects a duty error in an internal clock synchronized with an external clock and is capable of performing accurate duty measurement. A first capacitor is coupled to a first node and a first current sour... | 01/31/2012 |
| 8106696 | Duty ratio correction circuit and duty ratio correction method A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock sig... | 01/31/2012 |
| 8063684 | Pulse width modulated controller applied to switch-type voltage regulator A PWM controller applied to switch-type voltage regulator includes an error amplifier, a soft-start control circuit, a compensating load and a comparator. The error amplifier receives a reference voltage signal and a feedback voltage signal and outputs an error curr... | 11/22/2011 |
| 8022742 | Circuit for reducing duty distortion in a semiconductor memory device A circuit for outputting an amplified clock signal is disclosed. The circuit includes a first input terminal for inputting a first clock signal, a second input terminal for inputting a second clock signal, a first amplifier circuit for amplifying the first clock sig... | 09/20/2011 |
| 8018262 | Duty cycle correction circuit A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a f... | 09/13/2011 |
| 8018261 | Clock generator and methods using closed loop duty cycle correction Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized wi... | 09/13/2011 |
| 8008958 | Electronic device and method of correcting clock signal deviations in an electronic device A digital electronic device is provided which comprises a digital clock deviation detecting means and a digital clock correcting means. The clock deviation detecting means is used to detect a deviation of a first clock signal of the electronic device and/or the duty... | 08/30/2011 |
| 8004331 | CMOS clock receiver with feedback loop error corrections A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle e... | 08/23/2011 |
| 8004332 | Duty ratio control apparatus and duty ratio control method There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermi... | 08/23/2011 |
| 7999589 | Circuits and methods for clock signal duty-cycle correction Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution ... | 08/16/2011 |
| 7999588 | Duty cycle correction circuitry Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is su... | 08/16/2011 |
| 7994834 | Duty cycle corrector and clock generator having the same A duty cycle corrector includes a delay unit configured to adjust an input clock and an inverted input clock with a delay value controlled in response to one or more control signals and to generate a positive clock and a negative clock, and a duty detector configure... | 08/09/2011 |
| 7994835 | Duty control circuit and semiconductor device having the same A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltag... | 08/09/2011 |
| 7990195 | Duty cycle correction circuits having short locking times that are relatively insensitive to temperature changes A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal... | 08/02/2011 |
| 7986179 | Circuit and method for reducing popping sound A circuit for reducing popping sound comprises a waveform generator, a voltage accumulator, and a comparator. The waveform generator is configured for generating a periodic waveform, and the voltage accumulator is configured for generating an increased voltage. The ... | 07/26/2011 |
| 7982512 | Communication system communication device and method for determining duty ratio of PWM control A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a... | 07/19/2011 |
| 7977990 | Duty correction circuit, duty correction system, and duty correction method A duty correction circuit is provided which includes a level shifter receives complementary differential input signals having a duty ratio and controls levels of the differential input signals; a TrTf control circuit receives output signals of the level shifter and ... | 07/12/2011 |
| 7965118 | Method and apparatus for achieving 50% duty cycle on the output VCO of a phased locked loop Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting ... | 06/21/2011 |
| 7961023 | Pulse width modulation sequence maintaining maximally flat voltage during current transients A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or cu... | 06/14/2011 |
| 7961022 | Pulsed width modulated control method and apparatus A pulse width modulated (PWM) controller has an input terminal for receiving a pulsed input signal having a first duty cycle, a power supply terminal for receiving a power supply voltage. a minimum duty cycle reference voltage signal, and a control circuit for provi... | 06/14/2011 |
| 7956660 | Signal processing device A signal processing device includes a correction circuit configured to correct the distortion of the duty cycle in a data signal having different occurrence probabilities of 0 and 1. ... | 06/07/2011 |
| 7944262 | Duty correction circuit A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which d... | 05/17/2011 |
| 7940103 | Duty cycle correction systems and methods Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have fi... | 05/10/2011 |
| 7932761 | Fine tuned pulse width modulation Techniques and an apparatus for producing pulse width modulation (PWM) edges are described. A PWM controller circuit with a polyphase counter is described. The polyphase counter may comprise a plurality of counters. Each of the counters may be set to a specific init... | 04/26/2011 |
| 7928785 | Loop filter, phase-locked loop, and method of operating the loop filter A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty contr... | 04/19/2011 |
| 7920003 | Delay circuit with delay equal to percentage of input pulse width A delay circuit with a delay equal to the percentage of the input pulse width is described. In one embodiment, the ratio of the discharge current to the charge-up current of a timing capacitor is used to determine the percentage of the input pulse width used for the... | 04/05/2011 |
| 7920004 | Apparatus and method for duty cycle correction There is provided an apparatus for duty cycle correction. The apparatus for duty cycle correction comprises a moving sum unit performing a moving sum calculation with respect to the square-wave signal and outputting the moving sum signal subjected to moving sum calc... | 04/05/2011 |
| 7915939 | Duty cycle correction apparatus and semiconductor integrated circuit having the same A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and gene... | 03/29/2011 |
| 7913199 | Structure for a duty cycle correction circuit A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the... | 03/22/2011 |
| 7902893 | Clock-signal generator A clock-signal generating unit for generating an output clock signal with a controlled duty cycle based on an input clock signal. The clock-signal generating unit comprises one or more delay lines arranged to generate a plurality of mutually delayed output signals a... | 03/08/2011 |
