Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7420398 | Pulse extension circuits for extending pulse signals A pulse extension circuit for extending a pulse signal includes an input unit for receiving the pulse signal, an edge detection unit coupled to the input unit for generating a initiation signal, a pulse initiation unit coupled to the edge detection unit for outputti... | 09/02/2008 |
| 7372931 | Unit interval discovery for a bus receiver A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs register (SZERO) previously initialized to all ONES, and into respective ... | 05/13/2008 |
| 7372327 | Input structure for a power amplifier and associated methods A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to main... | 05/13/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7327181 | Multiple phase simultaneous switching preventing circuit, PWM inverter and its driving method A PWM inverter in which high-surge voltage is not applied across terminals of a switching device thereof is provided by preventing multi-phase simultaneous switching. A multi-phase simultaneous-switching prevention circuit (100) that includes: a plurality of ... | 02/05/2008 |
| 7319355 | Pulse generator A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first log... | 01/15/2008 |
| 7320081 | Clock-signal generation device, communication device, and semiconductor device A clock-signal generation device which changes an average frequency of a clock signal independently of a reference clock signal. A reference-clock-signal generation circuit generates a reference clock signal. A frequency-division circuit divides the frequency of the... | 01/15/2008 |
| 7317344 | Function selection circuit using a fuse option scheme A semiconductor device is provided as a fuse option circuit. The semiconductor device is configured to include an input, a function selection fuse portion and a reset control circuit portion both connected to the input, and an output connected to the function select... | 01/08/2008 |
| 7317341 | Duty correction device A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a pulse width of an input clock and output the adjusted clock as an outpu... | 01/08/2008 |
| 7317343 | Pulse-generation circuit with multi-delay block and set-reset latches In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and r... | 01/08/2008 |
| 7310010 | Duty cycle corrector A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is con... | 12/18/2007 |
| 7307461 | System and method for adaptive duty cycle optimization A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for... | 12/11/2007 |
| 7298193 | Methods and arrangements to adjust a duty cycle Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correc... | 11/20/2007 |
| 7282977 | Duty cycle correction device Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first si... | 10/16/2007 |
| 7245160 | Short pulse rejection circuit A short pulse rejection circuit is disclosed. The circuit comprises a signal transition detecting circuit, a control signal generating circuit, a capacitor resetting and charging circuit, and a charge pulse detecting circuit. The signal transition detecting circuit ... | 07/17/2007 |
| 7242233 | Simplified method for limiting clock pulse width The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pu... | 07/10/2007 |
| 7233199 | Circuit and method of establishing DC bias levels in an RF power amplifier A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noi... | 06/19/2007 |
| 7227387 | Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs... | 06/05/2007 |
| 7212045 | Double frequency signal generator A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An av... | 05/01/2007 |
| 7180347 | Systems and methods for minimizing harmonic interference Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the cloc... | 02/20/2007 |
| 7161427 | Input structure for a power amplifier and associated methods A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to main... | 01/09/2007 |
| 7154320 | Frequency-based slope-adjustment circuit A method and apparatus for a frequency-based slope-adjustment circuit block are described herein. ... | 12/26/2006 |
| 7154316 | Circuit for controlling pulse width Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode regist... | 12/26/2006 |
| 7091762 | Systems and methods for minimizing harmonic interference Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and a duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the cl... | 08/15/2006 |
| 7084685 | Method and related apparatus for outputting clock through a data path An output clock is provided by a logic module and at least one flip-flop based on a reference clock. Each flip-flop receives the reference clock at a corresponding clock end and changes a signal level outputted at a corresponding output port according to rising or f... | 08/01/2006 |
| 7064605 | Circuit and method of establishing DC bias levels in an RF power amplifier A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noi... | 06/20/2006 |
| 7042266 | Delay circuit and method A delay circuit does not lead to excessive increase in the delay time even if the source voltage drops, and enables to control the delay time from increasing. The delay circuit is designed to delay a logic signal SIN having two logic levels consisting of a low level... | 05/09/2006 |
| 7039147 | Delay locked loop circuitry for clock delay adjustment Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phas... | 05/02/2006 |
| 7030671 | Circuit for controlling pulse width The present invention discloses a circuit for controlling a pulse width including a frequency detection circuit for extracting an operation frequency band by receiving an external clock, delaying the external clock for a different time and comparing a frequency of t... | 04/18/2006 |
| 7026849 | Reset circuit having synchronous and/or asynchronous modules There is provided a reset circuit for reducing current consumption during resetting. A reset circuit 20 is constituted in such a manner that a pulse generation circuit 22 for generating a reset pulse signal (PRSTN) 50 from a reset signal input t... | 04/11/2006 |
| 7005893 | High-performance clock-powered logic High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam l... | 02/28/2006 |
| 6943711 | Frequency-digital signal conversion circuit There is provided a frequency-digital signal conversion circuit for automatically converting a clock frequency into a digital signal. The frequency-digital signal conversion circuit includes: a frequency detecting unit for detecting a frequency of an input clock sig... | 09/13/2005 |
| 6943556 | High-speed duty cycle test through DC measurement using a combination of relays According to one embodiment of the present invention, a method of high-speed duty cycle test through DC measurement using a combination of relays. The method includes: providing a plurality of relays to generate one or more duty cycle control signals; providing the ... | 09/13/2005 |
| 6924681 | Efficient pulse amplitude modulation transmit modulation Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a lo... | 08/02/2005 |
| 6919750 | Clock signal generation circuit used for sample hold circuit A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first contro... | 07/19/2005 |
| 6847244 | Variable duty cycle clock generation circuits and methods and systems using the same A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase o... | 01/25/2005 |
| 6833736 | Pulse generating circuit A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay t... | 12/21/2004 |
| 6828836 | Two comparator voltage mode PWM Two comparators are arranged to generate a pulse-width modulator (PWM) control pulse. The first comparator is arranged to start the PWM control pulse, while the second comparator is arranged to stop the PWM control pulse. The first comparator can be a high speed CMO... | 12/07/2004 |
| 6774692 | Apparatus and method for providing square wave to atomic force microscope An apparatus and method for providing an input signal having a desired pulse width and amplitude to atomic force miscoscopes (AFMs) for use in nano-lithography are provided. An input signal providing apparatus for a contact type AFM includes: a pulse width adjusting... | 08/10/2004 |
| 6753713 | System and method for expanding a pulse width A circuit and method for expanding the pulse width of a signal based on the input signal's pulse width. A circuit generates a delay equal to the pulse width of the input signal for both a SHIFT and OUT signal, which are out of phase with each other. The delay is gen... | 06/22/2004 |
