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| Number | Title | Issue Date |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7334152 | Clock switching circuit A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to... | 02/19/2008 |
| 7307461 | System and method for adaptive duty cycle optimization A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for... | 12/11/2007 |
| 7272742 | Method and apparatus for improving output skew for synchronous integrated circuits A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffer... | 09/18/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7230457 | Programmable dual drive strength output buffer with a shared boot circuit An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive outpu... | 06/12/2007 |
| 7170324 | Output buffer with selectable slew rate A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide... | 01/30/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7151394 | Phase shifting and PWM driving circuits and methods The present invention provides an inverter controller comprising a drive circuit that generates a plurality of switch drive signals for inverter applications. In some exemplary embodiments, the drive circuit operates by reversing the command level of an error signal... | 12/19/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7132858 | Logic circuit A logic circuit includes an input for one or several input operands, an output for a result and an inverted result, a first circuit branch with a first logic assembly, which is coupled to the input and the output, to calculate the result, as well as a second circuit... | 11/07/2006 |
| 7119602 | Low-skew single-ended to differential converter A single-ended to differential converter uses a cross-coupled latch that maximizes the output zero-crossing symmetry and is self compensating over PVT variations. An in-phase driving signal is provided by an always-on transmission gate coupled to the input. An out-o... | 10/10/2006 |
| 7119607 | Apparatus and method for resonance reduction A system is provided that includes a power distribution network to provide a switching current and a resonance reduction circuit to sense the switching current within a frequency range and to generate a resonance reduction signal having a current component at substa... | 10/10/2006 |
| 7113013 | Pulse generating circuit and sampling circuit There is provided a pulse generating circuit, which generates two pulses having a sign of amplitude different from each other, including: a step recovery diode of which electric potential of an anode and a cathode is respectively output as the pulses; a bias unit op... | 09/26/2006 |
| 7102416 | High side switching circuit A high side switching circuit, comprising: a switching transistor; a charge pump drive circuit including a circuit for generating an oscillating signal; and a charge pump arranged to provide a gate drive voltage to the switching transistor in response to a control s... | 09/05/2006 |
| 7088150 | Driver-side current clamping with non-persistent charge boost Under control of an input signal, a signal line is driven toward a first voltage by coupling a first current path to the signal line. While the first current path is coupled to the signal line, 1) a charge boost is provided to the signal line to increase the rate at... | 08/08/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7068727 | Halting data strobes on a source synchronous link and utilization of same to debug data capture problems Methods and apparatus for halting the data strobes transmitted over a source synchronous link to enable the data stored in the data capture flip-flops in a source synchronous receiver to be scanned out for subsequent analysis. This allows for the evaluation of the c... | 06/27/2006 |
| 7049857 | Asymmetric comparator for low power applications A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the... | 05/23/2006 |
| 7034733 | Switching circuitry Segmented mixed signal circuitry comprising a plurality of analog segments is disclosed. Each analog segment is operable to perform a series of switching operations dependent on an input data signal. The circuitry is arranged to receive shaped clock signals provided... | 04/25/2006 |
| 7023254 | Duty ratio corrector, and memory device having the same The present invention discloses a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for cor... | 04/04/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 7005903 | Output buffer with adjustment of signal transitions An output buffer generates an output signal having a plurality of low-to-high (LH) and high-to-low (HL) signal transitions, with each of the signal transitions having a clock-to-output delay. A pre-driver having a first and a second stage generates a reshaped wavefo... | 02/28/2006 |
| 6960948 | System with phase jumping locked loop circuit An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count val... | 11/01/2005 |
| 6959016 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the... | 10/25/2005 |
| 6954097 | Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ... | 10/11/2005 |
| 6952123 | System with dual rail regulated locked loop An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count val... | 10/04/2005 |
| 6952462 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 10/04/2005 |
| 6943603 | Pulse generating circuit and semiconductor device provided with same A pulse generating circuit generates a pulse with a desired pulse width even when a process parameter for manufacturing fluctuates or a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and o... | 09/13/2005 |
| 6931086 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 08/16/2005 |
| 6922091 | Locked loop circuit with clock hold function A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and th... | 07/26/2005 |
| 6911853 | Locked loop with dual rail regulation An apparatus having a dual rail regulated reference loop. The reference loop includes a delay circuit powered by upper and lower supply voltages to generate a plurality of reference clock signals, and a voltage regulation circuit to adjust the upper and lower supply... | 06/28/2005 |
| 6734709 | Method and system for performing sampling on the fly using minimum cycle delay synchronization A method and system for sampling on the fly one or more integrated circuit nodes coupled to one or more bus domain clocks of an integrated circuit using minimal clock cycle delay synchronization. Sample on the fly circuitry, set-reset circuitry and metastable reject... | 05/11/2004 |
| 6608513 | Flip-flop circuit having dual-edge triggered pulse generator A pulse generator system includes a plurality of buffers at least two transmission gates. The inverters successively and input insert delays into an signal having a series of pulses, each pulse having first and second edges. The transmission gates are ope... | 08/19/2003 |
| 6384658 | Clock splitter circuit to generate synchronized clock and inverted clock An apparatus, method and means for providing a clock signal and an inverted clock signal having corresponding rise and fall edge rates, being resistant to load variations, process variations, voltage variations, and temperature variations. The apparatus o... | 05/07/2002 |
| 6369615 | Semiconductor integrated circuit and pulse signal generating method The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input sig... | 04/09/2002 |
| 6256234 | Low skew differential receiver with disable feature A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the di... | 07/03/2001 |
| 6222422 | Method and apparatus for generating a symmetrical output signal from a non-symmetrical input A method of generating a symmetrical output signal with a 50% duty cycle. The symmetrical output signal is generated without the need for the input signal to be at twice the frequency of the output signal. By utilizing the differential output of a circuit... | 04/24/2001 |
| 6133771 | Device for generating pulses of high-precision programmable duration A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an outp... | 10/17/2000 |
| 6069511 | Digital slew rate and duty cycle control circuit and method A signal shaping circuit for use in a transmission line driver and the like is disclosed. The input is pulse signal having a rising edge that triggers a delay circuit which produces a first sequence of multiple delayed outputs and a falling edge which tri... | 05/30/2000 |
