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| Number | Title | Issue Date |
| 8174299 | Devices and methods for controlling a slew rate of a signal line In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate wil... | 05/08/2012 |
| 8169244 | Crossing input signal modulator The invention relates to a pulse width modulator, more particularly to a cross-coupled pulse width modulator. A crossing input signal modulator according to the present invention comprises: a positive path block which includes a first integrator for performing the f... | 05/01/2012 |
| 8067969 | Integrated circuit An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured... | 11/29/2011 |
| 8044693 | Output voltage slew rate control in hard disk motor drive A driver circuit includes a first transistor having a first node coupled to a high supply voltage and a second node coupled to an output node, wherein the first transistor passes the high supply voltage to the output node based on a first gate voltage on a gate of t... | 10/25/2011 |
| 8040171 | Accelerator output stage that adjusts drive duration to loading The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to... | 10/18/2011 |
| 8013648 | Output slew-rate controlled interface and method for controlling the output slew-rate of an interface An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, c... | 09/06/2011 |
| 8008957 | Inverting zipper repeater circuit Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described. ... | 08/30/2011 |
| 8004330 | Reduction of electromagnetic interference for differential signals Apparatus and methods modulate the slew rate of high-speed edges of a differential digital signal. High-speed digital signals carried over printed circuit boards, backplanes, cables, and the like can radiate electromagnetic waves. These electromagnetic waves can cau... | 08/23/2011 |
| 7999587 | Enhanced predistortion for slewing correction The present invention relates to a circuit arrangement and method of applying predistortion to a baseband signal used for modulating a pulse-shaped signal, wherein an envelope information of the baseband signal is detected and slewing distortions of the pulse-shaped... | 08/16/2011 |
| 7977989 | Method and apparatus for detecting and adjusting characteristics of a signal Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circui... | 07/12/2011 |
| 7969217 | Output buffer with slew-rate enhancement output stage An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second volt... | 06/28/2011 |
| 7940101 | Slew rate control for a load switch An apparatus for slew rate control using a plurality of discrete slew rate levels. The apparatus includes a load switch and a switch controller. The load switch outputs a load voltage to a load. The switch controller generates a switch control signal in response to ... | 05/10/2011 |
| 7940102 | Edge rate control for IC bus applications Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (... | 05/10/2011 |
| 7928784 | Method and apparatus to improve and control the propagation delay in a current slewing circuit A circuit for independently controlling slew and propagation delay of a current DAC is provided. The circuit applies dual slope technique with feed-back control the gate (or control electrode) of a switching transistor to make propagation delay independent control f... | 04/19/2011 |
| 7915937 | Circuitry and methods for improving differential signals that cross power domains Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain boundary along the output paths that generate the differential signal is staggered, such that the boundary occur... | 03/29/2011 |
| 7902892 | Method of control slope regulation and control slope regulation apparatus A control loop has a control slope associated therewith. The control loop is provided to control a unit under control. A method of regulating the control slope comprises the step of measuring the control slope of the control loop and modifying a parameter associated... | 03/08/2011 |
| 7880521 | Differential driver and method capable of controlling slew rate A differential driver includes first and second pull-up resistors respectively connected to first and second output terminals, a plurality of differential-input transistor pairs connected each to the first and second output terminals, current sources connected each ... | 02/01/2011 |
| 7868676 | Hybrid on-chip regulator for limited output high voltage A driver circuit includes a pre-driver and an output driver. The pre-driver is coupled to receive an input signal and to generate first and second pre-driver output signals in response to the input signal. The output driver generates a driver output signal and inclu... | 01/11/2011 |
| 7859317 | Low power high slew non-linear amplifier for use in clock generation circuitry for noisy environments Clock generation circuitry is arranged in stages so as to convert a slow slew rate input signal into a high slew rate clock signal in a low power environment. Each stage includes a capacitor and an inverter, both fed by respective current mirrors. The capacitor is t... | 12/28/2010 |
| RE41926 | Output circuit for adjusting output voltage slew rate The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an... | 11/16/2010 |
| 7804345 | Hybrid on-chip regulator for limited output high voltage A driver circuit provides fast settling times, slew rate control, and power efficiency, while reducing the need for large external capacitors. A voltage reference circuit generates a voltage reference signal. A comparator compares the voltage reference signal and a ... | 09/28/2010 |
| 7786778 | Output voltage slew rate control in hard disk motor drive A driver circuit includes a first transistor having a first node coupled to a high supply voltage and a second node coupled to an output node, wherein the first transistor passes the high supply voltage to the output node based on a first gate voltage on a gate of t... | 08/31/2010 |
| 7786779 | Buffer for driving circuit and method thereof A buffer for a driving circuit includes a first transistor, a second transistor and a slew rate controlling circuit. The first transistor serves to provide a current to an output terminal. The second transistor serves to sink a current from the output terminal. The ... | 08/31/2010 |
| 7772901 | Slew rate control circuit A slew rate control circuit is disclosed. An output impedance buffer and a slew rate buffer are coupled in parallel. An edge detector detects an input signal to accordingly control the output impedance buffer and the slew rate buffer, such that the input signal pass... | 08/10/2010 |
| 7759994 | Skew signal generation circuit and semiconductor memory device having the same In a skew signal generation circuit, a pad is connected to an external resistor and a code generator compares a voltage of the pad with a reference voltage to generate a plurality of codes. A skew signal extractor extracts a skew signal from the codes, the skew sign... | 07/20/2010 |
| 7737747 | Scheme for controlling rise-fall times in signal transitions A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitio... | 06/15/2010 |
| 7733142 | Edge rate control for 1C bus applications Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circ... | 06/08/2010 |
| 7728641 | Apparatus and method for outputting data of semiconductor memory apparatus An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that contr... | 06/01/2010 |
| 7696800 | Method and apparatus for detecting and adjusting characteristics of a signal Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circui... | 04/13/2010 |
| 7692463 | Devices and methods for controlling a slew rate of a signal line In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate wil... | 04/06/2010 |
| 7663418 | Driving circuit slew rate compensation method An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ... | 02/16/2010 |
| 7656209 | Output slew rate control This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are con... | 02/02/2010 |
| 7649392 | System for controlling a signal slew rate in a digital device A system for controlling a slew rate of a signal, such as used in an imaging device, comprises a counter for measuring a duration that the signal drops from a maximum voltage to a predetermined reference voltage; a register for retaining a desired duration that the ... | 01/19/2010 |
| 7646228 | Inverting zipper repeater circuit Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described. ... | 01/12/2010 |
| 7646229 | Method of output slew rate control This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are con... | 01/12/2010 |
| 7622972 | System and apparatus for generating ideal rise and fall time A system for generating an ideal rise or fall time includes: a first current source, for providing a first current; an adjustable capacitive component, coupled to the first current source, for generating an output signal according to a total capacitance controlled b... | 11/24/2009 |
| 7598784 | System and method for controlling signal transitions In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The... | 10/06/2009 |
| 7598785 | Apparatus and method for adjusting slew rate in semiconductor memory device A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control c... | 10/06/2009 |
| 7595674 | Universal serial bus (USB) driver circuit, system, and method A driver circuit, system, and method is provided. The driver circuit includes a plurality of delay cells or circuits, each comprising a set of flip-flop circuits coupled in series to produce a staged set of outputs onto an output port of the driver circuit. The stag... | 09/29/2009 |
| 7567105 | High speed controller area network receiver having improved EMI immunity A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver includes a voltage divider network connected to a front-end amplifier for dividing down the input signal from a... | 07/28/2009 |
