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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8122395 | On chip timing adjustment in multi-channel fast data transfer A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signal... | 02/21/2012 |
| 7920002 | Pulse synthesis circuit A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which a... | 04/05/2011 |
| 7915936 | Output signal error detection, circumvention, signal reconstruction and recovery A method of dealing with anomalies in an output signal is provided. The method includes monitoring transitions in the output signal. When transitions do not occur at expected times, detecting an anomalous signal. Determining the type of anomalous signal based at lea... | 03/29/2011 |
| 7414451 | Clock generator for semiconductor memory apparatus The clock generator for semiconductor memory apparatus which includes: a first divider; a first delay unit; a second divider; a second delay unit; a duty-cycle corrector; a third divider; a third delay unit; a phase comparator; and a delay time setting unit. The clo... | 08/19/2008 |
| 7375566 | Clock signal generator A clock signal generator includes a quartz crystal multivibrator circuit and a pulse-shaping circuit. The pulse-shaping circuit includes a D trigger. The D trigger includes a Q terminal, a Q′ terminal, a CP terminal, and a D terminal. An output signal from the qua... | 05/20/2008 |
| 7373572 | System pulse latch and shadow pulse latch coupled to output joining circuit In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data ... | 05/13/2008 |
| 7340633 | Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device (12), having the following steps: generation of a secondary clock (16) at a predeterm... | 03/04/2008 |
| 7328229 | Clock divider with glitch free dynamic divide-by change The circuit of this invention performs clock division with dynamic divide-by value change capability. This circuit provides low area and low latency. The clock divider is conventional except for the logic that handles the dynamic divide-by value change. When the div... | 02/05/2008 |
| 7320049 | Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode ... | 01/15/2008 |
| 7317343 | Pulse-generation circuit with multi-delay block and set-reset latches In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and r... | 01/08/2008 |
| 7304517 | Duty cycle corrector A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circui... | 12/04/2007 |
| 7295049 | Method and circuit for rapid alignment of signals Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of ... | 11/13/2007 |
| 7290158 | Method of controlling data transfer within a semiconductor integrated circuit based on a clock sync control signal A semiconductor integrated circuit device comprises an internal bus, a plurality of internal modules connected to the internal bus and including a main module performing a predetermined function, and a clock generating unit generating a reference clock and a clock s... | 10/30/2007 |
| 7279950 | Method and system for high frequency clock signal gating A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled p... | 10/09/2007 |
| 7274185 | Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices Pursuant to certain embodiments of the present invention, methods of generating an internal clock signal in a semiconductor memory device are provided in which the frequency of an external clock signal is measured. A CAS latency value of the semiconductor memory dev... | 09/25/2007 |
| 7260209 | Methods and apparatus for improving voice quality in an environment with noise A method for improving a downlink signal received by a listener on a phone is disclosed. The method includes calculating an environment noise level of the listener and filtering and adjusting gain of the downlink signal based on the environment noise level. ... | 08/21/2007 |
| 7253671 | Apparatus and method for compensating for clock drift in downhole drilling components A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded num... | 08/07/2007 |
| 7253661 | Method and apparatus for a configurable latch A configurable latch is implemented using a configurable pulse generator and a level sensitive (LS) latch. The configurable pulse generator produces either a pulse signal that is aligned with the input clock edge, or simply provides the input clock signal to its out... | 08/07/2007 |
| 7227375 | DAC based driver with selectable pre-emphasis signal levels A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added... | 06/05/2007 |
| 7203243 | Line driver with reduced power consumption A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors... | 04/10/2007 |
| 7202724 | Pulse-based flip-flop A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signa... | 04/10/2007 |
| 7187213 | Semiconductor circuit The present invention provides a semiconductor circuit capable of effectively applying a filter function to both of L-level noise superimposed during originally H signal periods and H-level noise superimposed during originally L signal periods. An input signal branc... | 03/06/2007 |
| 7184479 | Data transmission method and data transmission device A data transmission method capable of suppressing communication errors with a simple microcomputer processing is provided. Upon a pulse signal in which specific data is made up of H and L levels, either one of which has a pulse width taken as a first fundamental sig... | 02/27/2007 |
| 7177968 | Data transmission system In a data transmission system for carrying out data transmission/reception between a primary board and secondary boards by using a data transmission path, which employs a same signal line as an address bus and a data bus mutually, there are provided steps of informi... | 02/13/2007 |
| 7167996 | Micro controller unit It is an object to increase a speed of a CPU operation irrespective of an operation speed of a peripheral circuit and to prevent an increase in power consumption from being thereby caused. A clock generating circuit (10) generates two clocks having phases whi... | 01/23/2007 |
| 7154316 | Circuit for controlling pulse width Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode regist... | 12/26/2006 |
| 7154324 | Integrated circuit delay chains Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor m... | 12/26/2006 |
| 7129800 | Compensation technique to mitigate aging effects in integrated circuit components A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the... | 10/31/2006 |
| 7126396 | System for clock duty cycle stabilization A clock signal duty cycle stabilization system. The system includes a clock signal duty cycle stabilization circuit having an edge detection circuit and a latch circuit. The edge detection circuit is configured to receive an external clock signal and generate an out... | 10/24/2006 |
| 7102388 | Interface device and information processing system A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an electrically insulating area. A second converter circuit converts the pul... | 09/05/2006 |
| 7098726 | Method and apparatus for operating a voltage regulator based on operation of a timer In accordance with an embodiment of the disclosed matter, a voltage regulator may supply power to a component within a computer system. A timer may be provided. The voltage regulator may operate synchronously, and when the timer expires the voltage regulator may ope... | 08/29/2006 |
| 7081778 | Semiconductor integrated circuit related to a circuit operating on the basis of a clock signal A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input termina... | 07/25/2006 |
| 7064594 | Pass gate circuit with stable operation in transition phase of input signal, self-refresh circuit including the pass gate circuit, and method of controlling the pass gate circuit Provided is a pass gate circuit capable of operating stably in a transition phase of an input signal, a self-refresh circuit including the pass gate circuit, and a method of controlling the pass gate circuit. The pass gate circuit according to the present invention ... | 06/20/2006 |
| 7057434 | Circuit and method to eliminate startup and shutoff runt pulses from crystal oscillators A crystal oscillator circuit which does not produce runt pulses when the oscillator is turned on or off. The circuit includes a crystal oscillator, an integrator which integrates the energy in a plurality of pulses, a threshold circuit which is active when the outpu... | 06/06/2006 |
| 7053685 | Frequency signal enabling apparatus and method thereof The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pu... | 05/30/2006 |
| 7039143 | Circuit for determining the time difference between edges of a first digital signal and of a second digital signal The circuit has a first input for supplying a first signal (S1) to a series circuit made from a plurality of basic elements. Each basic element has a memory (M) for storing the signal level which is applied to the input of the basic element, and the output of... | 05/02/2006 |
| 7030676 | Timing circuit for separate positive and negative edge placement in a switching DC-DC converter A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a ... | 04/18/2006 |
| 7015600 | Pulse generator circuit and semiconductor device including same A pulse generator circuit is disclosed including a delay element coupled to a logic circuit. The delay element receives a clock signal CLK and a signal X and produces a signal XN dependent upon the clock signal CLK and the signal X. The logic circuit receives the cl... | 03/21/2006 |
| 7016284 | Method and related circuit for generating a wobble clock and an ATIP clock through a reference clock and a wobble signal A method and related circuit for clock generation and recovery utilizes digital components exclusively. The method is used to generate a wobble clock and an absolute time in pre-groove (ATIP) clock for controlling the operation of an optical disk drive. The circuit ... | 03/21/2006 |
| 6977522 | Interface device and information processing system A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an electrically insulating area. A second converter circuit converts the pul... | 12/20/2005 |
