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| Number | Title | Issue Date |
| 7876141 | Synchronization pulse generator with forced output A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended ... | 01/25/2011 |
| 7705646 | Threshold correction circuit, integrated circuit with threshold correction function, and circuit board with threshold correction function In order to monitor various types of noises which are to be introduced on signals through signal lines on a circuit board and automatically adjust the thresholds for signal state discriminations to make it possible to surely make a signal state discrimination withou... | 04/27/2010 |
| 7486121 | System and method for generating two effective frequencies using a single clock A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. W... | 02/03/2009 |
| 7436232 | Regenerative clock repeater A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to recei... | 10/14/2008 |
| 7429883 | Oscillator configured to complete an output pulse after inactivation An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving the control signal to generate the enable signal in response to an osci... | 09/30/2008 |
| 7397291 | Clock jitter minimization in a continuous time sigma delta analog-to-digital converter A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with a... | 07/08/2008 |
| 7359461 | Apparatus and method for recovering clock signal from burst mode signal There are provided an apparatus and method for recovering a clock signal from a burst mode signal. A first delay delays an input data signal for half of a time period of the input data signal, and produces a first delay signal. An XOR gate adds the input data signal... | 04/15/2008 |
| 7356785 | Optimizing IC clock structures by minimizing clock uncertainty A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a ... | 04/08/2008 |
| 7352816 | Data oversampling via clock and data interpolation An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second ... | 04/01/2008 |
| 7353420 | Circuit and method for generating programmable clock signals with minimum skew A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to th... | 04/01/2008 |
| 7342969 | Signaling with multiple clocks At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences occur out-of-phase with at least some of the reference times of anot... | 03/11/2008 |
| 7336219 | System and method for generating a radar detection threshold A method for generating a radar detection threshold includes computing a first plurality of percentile values associated with frequency domain values of frequency domain signals. The first plurality of percentile values is used to generate detection threshold values... | 02/26/2008 |
| 7332940 | Voltage hold circuit and clock synchronization circuit A voltage hold circuit which holds an input signal voltage includes a voltage comparator unit configured to output a result of comparison between a voltage of an externally inputted control signal and a voltage of an outputted analog hold signal, a digital value hol... | 02/19/2008 |
| 7323917 | Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase gene... | 01/29/2008 |
| 7315591 | Reproduced signal waveform processing apparatus A reproduced signal waveform processing apparatus is provided. The apparatus includes an A/D converter for sampling a reproduced signal at a reproducing clock having a predetermined oscillation frequency; a first equalizer for equalizing a digital reproduced signal ... | 01/01/2008 |
| 7310584 | Enhanced sonde recognition A detector for locating a sonde includes a plurality of antennas, an analogue to digital converter 11 and a digital signal processor to isolate the magnetic signal produced by the sonde. The digital signal processor includes a phase feedback loop 21 to... | 12/18/2007 |
| 7310794 | Backward compatible PLDs A computer-readable medium is encoded with a computer program for directing a computer to convert a first bitstream operable to configure, for example, an earlier-generation PLD to a second bitstream operable to configure, for example, a later-generation PLD, wherei... | 12/18/2007 |
| 7295607 | Method and system for receiving pulse width keyed signals Provided is a method to process a pulse width coded signal. the method includes digitizing a received pulse width coded signal and transforming the digitized signal to at least one of power domain and absolute value domain. The converting produces a converted signal... | 11/13/2007 |
| 7285988 | Comparator circuit with offset control A semiconductor integrated circuit has: a differential amplifier circuit including a first MOS transistor connected between a first node and a common node and a second MOS transistor connected between a second node and the common n... | 10/23/2007 |
| 7285998 | Duty ratio adjusting circuit A duty ratio adjusting circuit has a differential buffer (11) to produce a pulse signal (Dout) according to an input sine wave signal (Ain) and a reference voltage. The pulse signal is inverted and filtered to be supplied to a first analog buffer (14) ... | 10/23/2007 |
| 7284145 | Clock control circuit and integrated circuit A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the targ... | 10/16/2007 |
| 7276954 | Driver for switching device A driver for a switching device has a plurality of driver circuits for driving the switching device and a control circuit. The control circuit selectively operates the driver circuits in response to a plurality of predetermined drive modes. Alternatively, a driver f... | 10/02/2007 |
| 7271635 | Method and apparatus for reducing duty cycle distortion of an output signal A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output ... | 09/18/2007 |
| 7256635 | Low lock time delay locked loops using time cycle suppressor The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppr... | 08/14/2007 |
| 7256630 | System and method for PLL control Systems and methods for reducing the effects of the operation of logic on a phase-locked loop (PLL) circuit are disclosed. These systems and methods may allow a PLL circuit to compensate for the anticipated effects of an instruction before, substantially simultaneou... | 08/14/2007 |
| 7253671 | Apparatus and method for compensating for clock drift in downhole drilling components A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded num... | 08/07/2007 |
| 7248106 | Sampling signal amplifier A sampling differential amplifier for amplification of a signal having: a signal input (2) for application of an input signal to be amplified; signal amplification transistors (N1, N1) whose control connections are connected via sampling ... | 07/24/2007 |
| 7242233 | Simplified method for limiting clock pulse width The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pu... | 07/10/2007 |
| 7236551 | Linear half-rate phase detector for clock recovery and method therefor There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and... | 06/26/2007 |
| 7233215 | Frequency modulation circuit The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock sele... | 06/19/2007 |
| 7233185 | Vernier circuit for fine control of sample time A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temper... | 06/19/2007 |
| 7227396 | Clock signal input/output device for correcting clock signals The invention relates to a clock signal correction method, and to a clock signal input/output device into which a clock signal or a signal obtained therefrom is input and transmitted to a frequency divider, wherein a signal output by the frequency divider is transmi... | 06/05/2007 |
| 7221727 | All-digital phase modulator/demodulator using multi-phase clocks and digital PLL Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase r... | 05/22/2007 |
| 7222036 | Method for providing PVT compensation Delays through components of a programmable device are determined transparently to the user through the use of mimic paths. For each delay path to be measured, at least one mimic path is created that has similar components and characteristics to the actual path to b... | 05/22/2007 |
| 7212741 | Method of optimizing output signal of optical receiver using FEC and optical receiving system using the method Optical signals transmitted through an optical cable are converted into digital data of bits “1” and “0” on the basis of a reference voltage, and errors generated during transmission of the optical signals are corrected using Forward Error Correction (FEC). ... | 05/01/2007 |
| 7209008 | Multiple output phase-locked loop (PLL) using a single voltage controlled oscillator (VCO) Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment,... | 04/24/2007 |
| 7206370 | Clock recovery circuit A clock recovery circuit comprises a phase comparator detecting phase differences between input data and sampling clocks and outputs them as pulse signals of two values of advanced and delayed, a low-pass filter reducing frequencies of the pulse signals outputted fr... | 04/17/2007 |
| 7200769 | Self-compensating delay chain for multiple-date-rate interfaces Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an outpu... | 04/03/2007 |
| 7187727 | Clock and data recovery circuit and clock control method To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics. The clock and data recovery circuit includes a phase shift circuit 101 having a switch receiving as inputs multi-phase clocks f... | 03/06/2007 |
| 7184502 | Circuit arrangement for recovering clock and data from a received signal A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator for sampling the received signal in such a way that several sampling values of a bit cell transmitted with the received signal are distributed time-wise one aft... | 02/27/2007 |
