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| Number | Title | Issue Date |
| 8134394 | RF microwave circuit and pulse shaping method A multi-port circuit and corresponding method for simultaneous shaping of sub-nanosecond pulses (MCS3P). The MCS3P includes a coupled-line coupler, a Schottky detector diode, and circuitry for compressing the rising and falling edges of a wavef... | 03/13/2012 |
| RE41981 | Arbitrary waveform synthesizer to generate one or more arbitrary waveforms A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator i... | 12/07/2010 |
| 7439785 | Jitter producing circuitry and methods To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such paramete... | 10/21/2008 |
| 7424046 | Spread spectrum clock signal generation system and method A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spe... | 09/09/2008 |
| 7365577 | Noise waveform generator with spectrum control A waveform generator for generating a desired waveform is provided, including a noise kernel configured to store a plurality of samples from a predetermined waveform, the plurality of samples being assigned to a plurality of memory blocks; and an address arrangement... | 04/29/2008 |
| 7362835 | Clock generator circuit and related method for generating output clock signal The present invention discloses a clock generator circuit for generating an output clock signal. The clock generator circuit includes: a random frequency code generator for generating a frequency code randomly, wherein the random frequency code generator is clocked ... | 04/22/2008 |
| 7325021 | VLSI implementation of metastability-based random number generator using delay ladders A random number generator includes a chain of pairs of D-type flip-flops 205, 215 . . . having D and L inputs, a chain of substantially identical cascaded upper buffers 210,220 . . . each having a predetermined delay d1 and respective output... | 01/29/2008 |
| 7290154 | Probabilistic and introverted switching to conserve energy in a digital system A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized s... | 10/30/2007 |
| 7263470 | Digital gaussian noise simulator A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on... | 08/28/2007 |
| 7263505 | Method and apparatus for generating a sale offer over an electronic network system A method and apparatus are provided for generating a sale offer over an electronic network (such as the Internet). The method and apparatus may be used with a commercial sale system designed to increase the revenue income of Web site by offering, at a substantially ... | 08/28/2007 |
| 7243082 | Method and apparatus for generating a sale offer to selected individuals over electronic network systems A method and apparatus are provided for generating a sale offer over an electronic network (such as the Internet). The method and apparatus may be used with a commercial sale system designed to increase the revenue income of Web site by offering, at a substantially ... | 07/10/2007 |
| 7202712 | Multiphase resonant pulse generators A multiphase resonant pulse generator (74) has N groups of N−1 switches (44,46,48) which, when activated, form N paths from a power supply (Vdc) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes... | 04/10/2007 |
| 7154313 | Wideband spread spectrum clock A method and apparatus are described. The method comprises generating a clock signal comprising regularly spaced clock-timing transitions between a signal high and a signal low to provide timing for a circuit coupled to the clock signal, and periodicity-disrupting t... | 12/26/2006 |
| 7155626 | Data processor including clock thinning-out circuit A data processor which may prevent data processing being executed from being analyzed based on the power consumption has been disclosed. A data processor (100) may include clock generating circuit (101), a random number generating circuit (102),... | 12/26/2006 |
| 7139397 | Hybrid architecture for realizing a random numbers generator A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described. ... | 11/21/2006 |
| 7135904 | Jitter producing circuitry and methods To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such paramete... | 11/14/2006 |
| 7106115 | Arbitrary waveform synthesizer to generate one or more arbitrary waveforms A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator i... | 09/12/2006 |
| 7081846 | ECM techniques to counter pulse compression radar A system and method for generating a counter-measure signal in response to an incoming radar signal from a remote linear frequency modulated (LFM) pulse compression radar system. One method comprises the steps of receiving an incoming radar signal having a time peri... | 07/25/2006 |
| 7080106 | Random number generating method and random number generating device A random number generating method and a random number generating device are provided which are capable of generating uniform random numbers. Random pulses are generated by comparing a voltage level obtained by amplifying a voltage level of a thermal noise produced b... | 07/18/2006 |
| 7068788 | Data encryption for suppression of data-related in-band harmonics in digital to analog converters The present invention is related to digital to analog converter (DAC) input data encryption off-chip and decryption on-chip to suppress input data in-band harmonic leakage through package related parasitic capacitance. More specifically, the present invention relate... | 06/27/2006 |
| 7068786 | Dual use block/stream cipher A dual use block/stream cipher is provided with a first key section and a data section. The first key section is to be initialized with a first cipher key, and to successively transform the first cipher key or a modified version of the first cipher key. The data sec... | 06/27/2006 |
| 7049874 | Digital delaying device A digital delaying device for delaying an input signal includes a ring oscillator, a calibration unit, and at least one delay number calculation unit and delay channel. The ring oscillator includes loop-connected delay cells for outputting an oscillation clock. The ... | 05/23/2006 |
| 7034733 | Switching circuitry Segmented mixed signal circuitry comprising a plurality of analog segments is disclosed. Each analog segment is operable to perform a series of switching operations dependent on an input data signal. The circuitry is arranged to receive shaped clock signals provided... | 04/25/2006 |
| 7027499 | Detection and correction circuit for blind equalization convergence errors An apparatus processes an equalizer output signal. The equalizer output signal is formed by transmitting an alternate mark inversion input signal over a channel and passing the transmitted signal through an adaptive equalizer. The apparatus includes a correlator cir... | 04/11/2006 |
| 7023897 | Transmission circuit A transmission circuit includes a baseband circuit, spreading section, multiplier, digital modulator, quadrature modulator, and antenna. The baseband circuit generates and outputs at least one transmission data constituted by first and second channel data. The sprea... | 04/04/2006 |
| 7012948 | Method for assigning codes in uplink of synchronous wireless telecommunication system A method for assigning codes in an uplink of a synchronous code division multiple access (CDMA) telecommunication system is disclosed. The method for assigning a code in a reverse channel of a synchronous wireless telecommunication system, comprising the steps of: a... | 03/14/2006 |
| 7002425 | Pulse modulation A pulse modulator comprises a delay arrangement for receiving a first sequence of pulses and for delaying each received pulse several times to obtain a plurality of sequences of pulses having different phases. The pulse modulator further comprises a selection compon... | 02/21/2006 |
| 6999500 | System for direct sequence spreading A spreading system according to an embodiment of the invention spreads two data signals. The system produces a filtered signal that is based on one of the data signals and an output signal that is based on both of the data signals. In one example, a spreading system... | 02/14/2006 |
| 6985514 | Automatic gain control circuit and method for direct sequence spread spectrum receiver An automatic gain control circuit (3) for a direct sequence spread spectrum receiver. A discrimination unit (10) generates a discrimination signal error from received in-phase and quadrature base band signals, whilst multiplication unit (16) mul... | 01/10/2006 |
| 6980039 | DC-DC converter with noise spreading to meet spectral mask requirements A DC—DC converter includes a variable frequency oscillator, a control system and a power train. The DC—DC converter is well suited for use in a cell phone. The control system uses the output of the oscillator to control the power train. The oscillator varies its... | 12/27/2005 |
| 6965907 | Apparatus for generating random numbers An apparatus for generating random numbers includes a source for generating random quantum phenomena, a detector to detect instances of the random quantum phenomena, and a recorder to record the instances of the random quantum phenomena for use in generating random ... | 11/15/2005 |
| 6961426 | Cascaded stream cipher A pseudo-random number generating circuit and method, comprising: a plurality of pseudo-random number generator (PRNG) units combined in a cascade structure of several layers to produce a pseudo-random output stream, the PRNG units of any given layer running more sl... | 11/01/2005 |
| 6917223 | Gaussian noise generator A signal generator (10). The signal generator comprises circuitry (20) for producing at least a first input noise signal (N1), wherein the first input noise signal has a statistically insignificant autocorrelation. The signal generator also ... | 07/12/2005 |
| 6898262 | Programmable controller An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing sect... | 05/24/2005 |
| 6864730 | Clocked integrated semiconductor circuit and method for operating such a circuit An integrated semiconductor circuit having a number of circuit units which are driven by a clock signal and can be operated both in parallel and in series is provided. A connection supplying the clock signal is connected to the clock input of the respective circuit ... | 03/08/2005 |
| 6862483 | Apparatus for changing pulse width modulation at desired timing A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to... | 03/01/2005 |
| 6828841 | Clock receiver circuit for on-die salphasic clocking A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock di... | 12/07/2004 |
| 6781426 | Nanosecond monolithic CMOS readout cell A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the... | 08/24/2004 |
| 6771104 | Switching electronic circuit for random number generation A physical random number generator has a bi-stable latch that operates to latch a random number bit in response to a reception of a voltage oscillating signal. When a switching device is in a first operating state, the bi-stable latch is deactivated and an oscillato... | 08/03/2004 |
| 6753712 | Clock and data recovery circuit and clock control method thereof A clock and data recovery circuit includes a phase-shift circuit having a switch, which receives multiphase clocks, for selecting and outputting a plurality of clock pairs from among the multiphase clocks, and a plurality of interpolators, which receive the pluralit... | 06/22/2004 |
