Class 327/162 - Having reference source

Subclass of Class 327 - Miscellaneous active electrical nonlinear devices, circuits, and systems
Definition: Subject matter wherein a clock is used as a standard.
No. of patents: 133
Last issue date: 09/22/2009

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Number	Title	Issue Date
7592847	Phase frequency detector and phase-locked loop A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. Th...	09/22/2009
7443213	Staged locking of two phase locked loops Data synchronization is achieved in devices which transmit and/or receive audio and/or video data through the staged locking of phase locked loops. According to an exemplary embodiment, a transmitter includes a serial data source. An encoder provides encoded data an...	10/28/2008
7424046	Spread spectrum clock signal generation system and method A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spe...	09/09/2008
7421048	System and method for multimedia delivery in a wireless environment A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing ...	09/02/2008
7402821	Application of digital frequency and phase synthesis for control of electrode voltage phase in a high-energy ion implantation machine, and a means for accurate calibration of electrode voltage phase An improved HE LINAC-based ion implantation system is disclosed utilizing direct digital synthesis (DDS) techniques to obtain precise frequency and phase control and automated electrode voltage phase calibration. The DDS controller may be used on a multi-stage linea...	07/22/2008
7352217	Lock phase circuit Systems and techniques for producing a signal with a known phase relationship to a source clock at an output of an indeterminate circuit element such as a clock divider. The systems and techniques may be used to allow circuit test data to be accurately compared with...	04/01/2008
7349510	Apparatus for data recovery in a synchronous chip-to-chip system An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing refe...	03/25/2008
7310010	Duty cycle corrector A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is con...	12/18/2007
7295053	Delay-locked loop circuits A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number ...	11/13/2007
7253671	Apparatus and method for compensating for clock drift in downhole drilling components A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded num...	08/07/2007
7248661	Data transfer between phase independent clock domains An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the arrangement comprising: a data transfer buffer for buffering a data strea...	07/24/2007
7191081	Method for correcting an oscillator frequency A method for correcting an oscillator frequency of in particular a digital transmitter/receiver interface for transmitting measurement signals of a sensor to a control unit. The method includes outputting of a first reference frequency signal by the sensor, the firs...	03/13/2007
7176738	Method and apparatus for clock generation A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset values(s), and combinations of such. ...	02/13/2007
7171323	Integrated circuit having clock trim circuitry An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the num...	01/30/2007
7149145	Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de...	12/12/2006
7145373	Frequency-controlled DLL bias A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitu...	12/05/2006
7138611	Heating structure and its temperature control method A heating structure and its temperature control method having therein a heat generating line and a controller. The heat generating line includes a PTC element and a short circuit line serially connected having an insulating fusible layer separating them. When a user...	11/21/2006
7126398	Method and an apparatus to generate static logic level output A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The app...	10/24/2006
7106113	Adjustment and calibration system for post-fabrication treatment of phase locked loop input receiver An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a ...	09/12/2006
7096137	Clock trim mechanism for onboard system clock An integrated circuit, comprising a processor, an onboard system clock for generating a clock signal, and clock trim circuitry, the integrated circuit being configured to: (a) receive an external signal; (b) determine either the number of cycles of the clock signal ...	08/22/2006
7091795	Modulating ramp angle in a digital frequency locked loop A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable both to clock a pr...	08/15/2006
7079611	System and method for synchronizing an asynchronous frequency for use in a digital system A system and method for accurately detecting an asynchronous frequency within a synchronous digital system. The improved system and method preconditions the asynchronous frequency so that it does not introduce additional phase noise at low frequencies within a digit...	07/18/2006
7050467	Digital-to-phase-converter A digital-to-phase or digital-to-time-shift converter (100) includes a delay line (106), a multiplexor (108) and synchronization circuit (110). In the converter (100) the clock edges of a reference signal are shifted in response to...	05/23/2006
7010436	Method and device for prediction of a zero-crossing alternating current An apparatus (14) for detecting a zero-crossing of an alternating current after occurrence of a fault in a current path (2) for determining a suitable time for opening an electric switching device (2) arranged in the current path for breaking th...	03/07/2006
7002415	Frequency locked loop A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable to both clock a pr...	02/21/2006
6985016	Precision closed loop delay line for wide frequency data recovery A closed loop delay line system (700) includes a phase lock loop that provides a phase lock output signal (715). A delay line (702) includes a clock input, a delay line output, and a delay line bias input. A bias signal provided to the delay lin...	01/10/2006
6982578	Digital delay-locked loop circuits with hierarchical delay adjustment Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers ha...	01/03/2006
6976184	Clock forward initialization and reset signaling technique A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A seco...	12/13/2005
6956419	Fail-safe zero delay buffer with automatic internal reference An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal...	10/18/2005
6954091	Programmable phase-locked loop An integrated circuit is provided, which includes a phase-locked loop (PLL) that is fabricated on the integrated circuit and has a selectable loop filter capacitance and a selectable output frequency range. ...	10/11/2005
6952124	Phase locked loop circuit with self adjusted tuning hiep the pham A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, one or more second inputs to receive one or more tuning range control signals, and an output to provide an oscillation output signal, ...	10/04/2005
6900676	Clock generator for generating accurate and low-jitter clock A clock generator has a clock generating circuit, a phase difference detection circuit, and a control signal generating circuit. The clock generating circuit has a function for varying a clock phase in accordance with a control signal, the phase difference detection...	05/31/2005
6900683	Apparatus and method for generating a predetermined time delay in a semiconductor circuit A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of ...	05/31/2005
6891417	Circuits and methods for alignment of signals in integrated circuits Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on ...	05/10/2005
6873195	Compensating for differences between clock signals A clock compensation circuit is provided. The circuit comprises a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signa...	03/29/2005
6862332	Clock reproduction circuit A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4	03/01/2005
6836167	Techniques to control signal phase A phase locked loop that may use UP and/or DN signals having programmable active state durations to control the speed of a clock signal. ...	12/28/2004
6809564	Clock generator for an integrated circuit with a high-speed serial interface The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention...	10/26/2004
6791380	Universal clock generator The present invention discloses a universal clock generator, which comprises a high frequency clock region for generating high frequency clocks and a low frequency clock region for generating high frequency clocks. The low frequency clock region includes at least on...	09/14/2004
6792060	Processor having an adaptable operational frequency The invention relates to a processing device for digital data which is capable of processing data which have been sampled with a sampling clock which may have any value whatsoever with respect to the basic clock of the device. To achieve this, the device is provided...	09/14/2004

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Class 327/162 - Having reference source