Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7009433 | Digitally controlled delay cells Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applicati... | 03/07/2006 |
| 7010014 | Digital spread spectrum circuitry The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly di... | 03/07/2006 |
| 7009434 | Generating multi-phase clock signals using hierarchical delays Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD inclu... | 03/07/2006 |
| 7005904 | Duty cycle correction A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal havin... | 02/28/2006 |
| 6998889 | Circuit, apparatus and method for obtaining a lock state value A circuit, apparatus and method provides a lock state value representing an amount of time a phase alignment circuit (“PAC”), such as a PLL or DLL, is tracking or locked to an incoming reference signal for a predetermined period of time. In an embodiment of the ... | 02/14/2006 |
| 6999547 | Delay-lock-loop with improved accuracy and range A Delay-Lock-Loop circuit and a method for producing a phase shift comprises a phase generator producing a first and second clock signal having a first and second rising edge, respectively, wherein a timing difference between the first and second rising edges is equ... | 02/14/2006 |
| 6998892 | Method and apparatus for accommodating delay variations among multiple signals A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines between different levels are detected. The timing of a signal affecting re... | 02/14/2006 |
| 6996201 | Data receiving system robust against jitter of clock A plurality of delay circuits successively delay a received data. The received data and delayed data signals are sampled in response to both leading and trailing edges of a clock having a frequency substantially identical with that of a data transmission rate of the... | 02/07/2006 |
| 6995586 | Monotonic leakage-tolerant logic circuits An improved logic methodology that combines the speed advantages of dynamic logic with the low contention of static logic, such that the logic circuits are not adversely affected by high-leakage transistors. The logic circuit of the present invention comprises first... | 02/07/2006 |
| 6992514 | Synchronous mirror delay circuit and semiconductor integrated circuit device having the same Disclosed is a synchronous mirror delay circuit for generating an internal clock signal synchronized with an external clock signal, comprising: a clock buffer circuit that generates a reference clock signal in response to the external clock signal; a delay monitor c... | 01/31/2006 |
| 6987700 | Method and system for writing data to a memory Methods and systems consistent with this invention write data to a memory. Such methods and systems may generate a clock signal, generate an intermediate clock signal from the clock signal using a clock tree buffer, delay the intermediate clock signal to form a data... | 01/17/2006 |
| 6987409 | Analog delay locked loop with tracking analog-digital converter An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping c... | 01/17/2006 |
| 6987408 | Digital delay locked loop and control method thereof There is provided a digital delay locked loop (DLL) which is capable of minimizing a jitter by predicting and detecting a maximum jitter timing. The digital delay locked loop includes: a clock generator for generating a source clock and a reference clock; a delay li... | 01/17/2006 |
| 6982579 | Digital frequency-multiplying DLLs Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of uni... | 01/03/2006 |
| 6982578 | Digital delay-locked loop circuits with hierarchical delay adjustment Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers ha... | 01/03/2006 |
| 6980480 | Multi-frequency synchronizing clock signal generator An apparatus and method for generating a plurality of synchronizing signals for synchronizing operation of the device in which the apparatus is located, such as in semiconductor memory devices. The apparatus can generate a plurality of synchronizing signals based on... | 12/27/2005 |
| 6980040 | Delay adjusting apparatus providing different delay times by producing a plurality of delay control signals The present invention relates to a semiconductor device; and, more particularly, to a delay adjusting circuit which is required to adjust a delay time of an internal circuit in a test mode and required to verify a characteristic and a margin of the semiconductor dev... | 12/27/2005 |
| 6977529 | Differential clock signal detection circuit A semiconductor integrated circuit includes a first clock input and a second clock input to receive elements of a differential clock signal. Each clock signal element has a logic state. The circuit generates an output activation signal that depends on the states of ... | 12/20/2005 |
| 6975695 | Circuit for correction of differential signal path delays in a PLL An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) select one of a plurality of input signals and (ii) generate (a) an output signal having a frequency and (b) one or more control signals in response to a skew si... | 12/13/2005 |
| 6970029 | Variable-delay signal generators and methods of operation therefor A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase ... | 11/29/2005 |
| 6970047 | Programmable lock detector and corrector An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally c... | 11/29/2005 |
| 6970313 | Write compensation circuit and signal interpolation circuit of recording device A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying porti... | 11/29/2005 |
| 6970521 | Circuit and system for extracting data A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is b... | 11/29/2005 |
| 6968026 | Method and apparatus for output data synchronization with system clock in DDR A method and apparatus for substantially reducing or eliminating the timing skew caused by delay elements in a delay locked loop. A method and apparatus is disclosed wherein a rising edge of a local timing signal is established and phase-locked to a rising edge of a... | 11/22/2005 |
| 6967536 | Phase-locked loop circuit reducing steady state phase error A phase-locked loop circuit has a DLL circuit in a stage preceding an analog PLL circuit. The DLL circuit detects a phase difference between a reference clock signal and a feedback signal, changes the detected phase difference to a phase difference increased so as t... | 11/22/2005 |
| 6964003 | Integrated circuit testing system and method A system and method for testing the data propagation time in an integrated circuit at relatively low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided... | 11/08/2005 |
| 6963235 | Delay locked loop circuit with duty cycle correction function A delay locked loop (DLL) circuit having a structure in which a method of performing duty cycle correction (DCC) using two DLLs and an intermediate phase composer and a method of performing DCC by forming a closed loop using a negative feedback are combined with eac... | 11/08/2005 |
| 6960948 | System with phase jumping locked loop circuit An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count val... | 11/01/2005 |
| 6960950 | Circuit and method for generating a clock signal In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a plurality of selectable delay circuits. The control circuit receives the clock signal from the oscillator and a refere... | 11/01/2005 |
| 6958592 | Adaptive delay control circuit for switched mode power supply A switched mode power supply comprises a first switch coupled to an input power source, a second switch coupled to ground, and an output filter coupled to a phase node defined between the first and second switches. The first and second switches are responsive to a p... | 10/25/2005 |
| 6959016 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the... | 10/25/2005 |
| 6956418 | Delay locked loop device A delay locked loop device includes a first delay line for receiving an external clock signal and a first delay control signal to generate a first internal clock signal; a second delay line for receiving the external clock signal and a second delay control signal or... | 10/18/2005 |
| 6954093 | Clocking scheme and clock system for a monolithic integrated circuit Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c0) generated by a clock source which is coupled to N intermediate clocks (c1 through cN) which are delayed relative to each other, wherein the individual delays (t) a... | 10/11/2005 |
| 6954094 | Semiconductor memory device having partially controlled delay locked loop A semiconductor memory device having a partially controlled delay locked loop includes a delay locked loop and a control signal generator. The control signal generator generates a first control signal and a second control signal, which are responsive to first throug... | 10/11/2005 |
| 6954095 | Apparatus and method for generating clock signals A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first tim... | 10/11/2005 |
| 6954097 | Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ... | 10/11/2005 |
| 6952123 | System with dual rail regulated locked loop An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count val... | 10/04/2005 |
| 6952127 | Digital phase mixers with enhanced speed Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the... | 10/04/2005 |
| 6952431 | Clock multiplying delay-locked loop for data communications In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provi... | 10/04/2005 |
| 6952462 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 10/04/2005 |
