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A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.
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| Number | Title | Issue Date |
| 4514647 | Chipset synchronization arrangement Each chip of a microprocessor chipset is synchronized by an associated controller which adjusts a control signal for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by ... | 04/30/1985 |
| 4496861 | Integrated circuit synchronous delay line A synchronized delay line is described which is tapped to provide a plurality of timing signals. The delay line is insensitive to voltage changes, temperature changes and wafer processing variations. It is ideally suited for providing on-chip timing signa... | 01/29/1985 |
| 4476401 | Write strobe generator for clock synchronized memory An on-chip memory control circuit generates a proper WRITE STROBE signal for a clock synchronized pipe-line operated integrated circuit memory. A symmetrical clock signal having half the frequency of the system clock is produced by applying the system clo... | 10/09/1984 |
| 4453259 | Digital synchronization technique Method and apparatus for providing a sequence of digitized samples to a modem in substantial synchronism with the incoming signal baud rate, but without using a variable sampling frequency. An incoming signal is sampled at a fixed rate, stored temporarily... | 06/05/1984 |
| 4408333 | Data acquisition circuit A data acquisition circuit is adapted to receive information data, a synchronization pulse and a clock pulse which is transmitted at twice as high as the transmission rate of the information data. The clock and synchronization pulses are processed into a ... | 10/04/1983 |
| 4386323 | Arrangement for synchronizing the phase of a local clock signal with an input signal Synchronizing the phase of a locally generated clock signal with the phase of an input signal is usually effected by using a phase-locked loop, but this has a drawback that a certain run-in time is necessary to be sure that the phase of the clock signal i... | 05/31/1983 |
| 4379974 | Delay stage for a clock generator A delay stage (30,50) receives input signals at input terminal (16) and power from power terminals (12, 14). A detector circuit (30) is connected between power terminals (12, 14) and to the input terminal (16) for receiving the input signal and for genera... | 04/12/1983 |
| 4380083 | Method of and an arrangement in a telecommunication system for regulating the phase position of a controlled signal in relation to a reference signal The invention relates to a method for regulating the phase position of a controlled signal in relation to the phase position of a reference signal in a telecommunication system, and an arrangement for carrying out the method. A reference signal (C2) is de... | 04/12/1983 |
| 4358741 | Micro time and phase stepper A digital time phase shifter for shifting a signal in very precise increments and which performs the steps of: mixing a reference frequency signal with the signal to be time or phase delayed for generating an intermediate frequency signal; selectively del... | 11/09/1982 |
| 4320525 | Self synchronizing clock derivation circuit for double frequency encoded digital data A circuit for accurately reconstructing the timing information encoded within digital waveforms of the double frequency class includes facilities for restoring the circuit to proper synchronization at start up time or after a burst of noise on an incoming... | 03/16/1982 |
| 4320515 | Bit synchronizer A bit synchronizer for T-4 fiber optic data communication environments is configured of an input buffer amplifier to which the data to be regenerated is applied. The input buffer provides isolation between upstream signal processing circuitry and a bit ra... | 03/16/1982 |
| 4287437 | Method and circuitry for equalizing the differing delays of semiconductor chips For equalizing the signal delay times of semiconductor chips a digital control circuit is provided on each chip. By altering the supply voltage, the digital control circuit influences the signal delay times. The digital control circuit comprises a comparator c... | 09/01/1981 |
| 4196398 | Regulation of a plurality of superconducting resonators In order to maintain a plurality of superconducting resonators, each having elastically deformable resonant structural elements, at the same natural frequency and phase position, each resonator is supplied with high frequency power independently of the ot... | 04/01/1980 |
| 4134073 | Clock system having adaptive synchronization feature A clock cycle is provided by a delay device, the output of which is coupled via an inverter to the input thereof, which inverter is combined in a gate structure so as to enable such clock cycle and derivative clock pulses coupled to be generated as a sign... | 01/09/1979 |
| 4084233 | Microcomputer apparatus A computer system features a processor unit which includes its own microprogram control unit. The microprogram control unit includes a storage means for operational instructions for the processor unit and means to issue those instructions in a desired seq... | 04/11/1978 |
| 4061933 | Clock generator and delay stage A clock generator for an MOSFET integrated circuit having a plurality of cascaded delay stages is disclosed. Each delay stage includes a bootstrap inverter having first and second transistors connected in series between the drain supply voltage and a sour... | 12/06/1977 |
| 4021740 | Sinewave clock driver with adjustable delay A sinewave clock distribution network and a clock driver for use in the network permit simplified distribution and synchronization in very high speed logic and digital transmission systems. The sinewave central clock is connected through a branching netwo... | 05/03/1977 |
| 3982194 | Phase lock loop with delay circuits for relative digital decoding over a range of frequencies In a feedback control system wherein data pulses also establish timing coordination between the data and the processing devices, two delay circuits are provided to extract the synchronized clock pulses from the coded incoming signal. This enables relative... | 09/21/1976 |
