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| Number | Title | Issue Date |
| 7417478 | Delay line circuit Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay ... | 08/26/2008 |
| 7414451 | Clock generator for semiconductor memory apparatus The clock generator for semiconductor memory apparatus which includes: a first divider; a first delay unit; a second divider; a second delay unit; a duty-cycle corrector; a third divider; a third delay unit; a phase comparator; and a delay time setting unit. The clo... | 08/19/2008 |
| 7414446 | DLL circuit of semiconductor memory apparatus and method of delaying and locking clock in semiconductor memory apparatus A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock b... | 08/19/2008 |
| 7414444 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 08/19/2008 |
| 7405604 | Variable delay clock circuit and method thereof An apparatus for generating an output clock is disclosed. The apparatus comprises: N variable offset clock circuits for receiving N input clocks and for generating N intermediate clocks having N phase offsets controlled by N intermediate signals, respectively, where... | 07/29/2008 |
| 7403054 | Sub-picosecond multiphase clock generator A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, whi... | 07/22/2008 |
| 7403056 | Delay apparatus and method thereof The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of d... | 07/22/2008 |
| 7400211 | High speed passband phase modulation apparatus and method of the same A high speed passband phase modulation apparatus and method are provided. In the phase modulation apparatus, an RF phase shifter modulates a phase of a local signal that is generated in a VCO according to a digital input. The RF phase shifter is controlled by a phas... | 07/15/2008 |
| 7397289 | Skew adjusting method, skew adjusting apparatus, and test apparatus There is provided a skew adjusting apparatus for adjusting a skew between a positive-side differential signal and a negative-side differential signal in differential signals inputted from an outside device via outside transmission lines, having a positive-side trans... | 07/08/2008 |
| 7391246 | Digital high speed programmable delayed locked loop A digital high speed programmable delayed locked loop (DLL) includes a zero degree phase shift digital delay line, at least one intermediate phase shift digital delay line, a three hundred and sixty degree phase shift digital delay line, and a digital control module... | 06/24/2008 |
| 7388442 | Digitally controlled oscillator for reduced power over process variations This disclosure relates to a cell-placeable variable-frequency digitally controlled oscillator (DCO) that consumes approximately the same current in a fast process corner as in the case of a slow process corner. By modulating the effective channel length of transist... | 06/17/2008 |
| 7388412 | Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock A clock multiplier includes a phase-locked loop (PLL), a bias generator, a counter, a selection circuit, a flip-flop, a phase comparator, a delay controller and a variable delay circuit. The variable delay circuit, which is biased by a delay cell bias signal, delays... | 06/17/2008 |
| 7382678 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 06/03/2008 |
| 7379521 | Delay circuit with timing adjustment function In a phase locked loop circuit, a phase comparator compares the phase of input clock and that of output clock, and provides a control signal as the comparison result. A charge pump circuit includes a clamp circuit, and based on the control signal, provides a control... | 05/27/2008 |
| 7378891 | Measure-controlled circuit with frequency control Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path generates a second clock signal based on the first clock signal. The delay locked circuit periodically p... | 05/27/2008 |
| 7375564 | Time delay compensation circuit comprising delay cells having various unit time delays A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includ... | 05/20/2008 |
| 7375593 | Circuits and methods of generating and controlling signals on an integrated circuit Embodiments of the present invention include an integrated circuit comprising an integrated transmission line, wherein the integrated transmission line is used as a timing reference for a feedback loop and wherein the feedback loop and the transmission line are inte... | 05/20/2008 |
| 7375565 | Delay locked loop in semiconductor memory device A delayed lock loop for preventing a stuck fail in a dead-zone includes a clock buffering block for generating a first and a second internal clock signals; a phase comparison block for delaying a feedback signal by a first predetermined value and for respectively co... | 05/20/2008 |
| 7375558 | Method and apparatus for pre-clocking A method and apparatus for pre-clocking have been disclosed. ... | 05/20/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372310 | Digital frequency-multiplying DLLs Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of uni... | 05/13/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7368963 | Delay locked loop for use in semiconductor memory device and method thereof A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locke... | 05/06/2008 |
| 7368965 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 05/06/2008 |
| 7366270 | PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a ... | 04/29/2008 |
| 7365728 | Shift register and display device A display device is provided with a shift register having a plurality of bistable circuits, each of the bistable circuits being connected to a corresponding scanning line. An RS flip-flop circuit provided in each of the bistable circuits functions as a memory portio... | 04/29/2008 |
| 7359407 | Data interface that is configurable into separate modes of operation for sub-bit de-skewing of parallel-fed data signals A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication system and can be configured to operate in one of three possible modes of... | 04/15/2008 |
| 7352218 | DLL circuit and method of controlling the same A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is... | 04/01/2008 |
| 7353418 | Method and apparatus for updating serial devices The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the ... | 04/01/2008 |
| 7352253 | Oscillator circuit with tuneable signal delay means The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit fu... | 04/01/2008 |
| RE40205 | Semiconductor device and timing control circuit Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A sig... | 04/01/2008 |
| 7352313 | Method and apparatus for master/slave digital-to-analog conversion Methods and apparatus are provided for improved digital-to-analog conversion. The disclosed digital-to-analog converter comprises a master digital-to-analog converter that generates a master analog value, and a slave digital-to-analog converter that generates a slav... | 04/01/2008 |
| 7349510 | Apparatus for data recovery in a synchronous chip-to-chip system An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing refe... | 03/25/2008 |
| 7346139 | Circuit and method for generating a local clock signal A circuit and method for generating a local clock signal and a telecommunications system incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a phase detector for receiving an input data signal, (2) (at least) first and second contin... | 03/18/2008 |
| 7339408 | Generating multi-phase clock signals using hierarchical delays Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD inclu... | 03/04/2008 |
| 7336548 | Clock generating circuit with multiple modes of operation A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by... | 02/26/2008 |
| 7336106 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 02/26/2008 |
| 7336111 | Fast-locking digital phase locked loop An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is... | 02/26/2008 |
| 7336112 | False lock protection in a delay-locked loop (DLL) A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicat... | 02/26/2008 |
| 7330060 | Method and apparatus for sigma-delta delay control in a delay-locked-loop Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and... | 02/12/2008 |
