Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 6882195 | Signal timing adjustment circuit with external resistor A semiconductor device includes an external resistor for establishing a delay of a signal relative to another signal in the device. The resistor may be external to a buffer, such as a zero-delay buffer, that receives an input signal generates one or more output sign... | 04/19/2005 |
| 6879541 | Integrated circuit with improved output control signal and method for generating improved output control signal In a semiconductor integrated circuit, the internal clock that is synchronized to the external clock is counted to output data according to desired specification of the integrated circuit and clock counting in high frequency operation is made be possible by using pa... | 04/12/2005 |
| 6879196 | System and method for compensating for supply voltage induced clock delay mismatches Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees... | 04/12/2005 |
| 6876239 | Delay locked loop “ACTIVE command” reactor A delay locked loop (DLL) that applies an amount of delay to an external clock signal to generate multiple delayed signals. One of the delayed signals is selected as an internal clock signal. The multiple delayed signals have different delays in relation to the exte... | 04/05/2005 |
| 6867626 | Clock synchronization circuit having bidirectional delay circuit strings and controllable pre and post stage delay circuits connected thereto and semiconductor device manufactured thereof A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable... | 03/15/2005 |
| 6865121 | Programmable delay circuit within a content addressable memory An apparatus including a content addressable memory (CAM) array, a clocked circuit coupled to the CAM array, and a programmable delay circuit coupled to receive a reference clock signal and generate a programmable delayed clock signal using a delay element for the c... | 03/08/2005 |
| 6861886 | Clock deskew protocol using a delay-locked loop A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample dat... | 03/01/2005 |
| 6862332 | Clock reproduction circuit A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4 | 03/01/2005 |
| 6859404 | Apparatus and method of compensating for phase delay in semiconductor device An apparatus for minimizing a skew occurring due to a change of data pattern by previously recognizing data pattern before data is outputted from the semiconductor device. The apparatus of compensating for a phase delay in a semiconductor device having a delay locke... | 02/22/2005 |
| 6857081 | Apparatus suitable for providing synchronized clock signals to a microelectronic device A device for transmitting clock signals to a microprocessor is disclosed. The device is configured to receive a clock signal and distribute the signal synchronically to multiple output sites on the device. The synchronized clock signals are transmitted from the vari... | 02/15/2005 |
| 6853226 | Register controlled delay locked loop having an acceleration mode A register controlled delay locked loop having an acceleration mode corresponding to an increase of the operation speed of a memory device is used to improve accuracy. The register controlled delay locked loop includes a delay line, a delay model, a delay block, a f... | 02/08/2005 |
| 6847238 | Output circuit and method for reducing simultaneous switching output skew An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a de... | 01/25/2005 |
| 6847241 | Delay lock loop using shift register with token bit to select adjacent clock signals Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multip... | 01/25/2005 |
| 6845458 | System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the ... | 01/18/2005 |
| 6845459 | System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the ... | 01/18/2005 |
| 6842057 | Analog state recovery technique for DLL design A method and apparatus stores a voltage potential generated by a delay locked loop in order to reduce the time required for the delay locked loop to recover from a lost clock state. A clock path is arranged to carry a clock signal. The delay locked loop operatively ... | 01/11/2005 |
| 6838917 | Circuit configuration for processing data, and method for identifying an operating state A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the... | 01/04/2005 |
| 6836165 | DLL circuit and method of generating timing signals A DLL circuit includes a delay circuit, a phase comparing circuit and a delay control circuit. The delay circuit is connected to first and second nodes, and delays an original clock signal supplied to the first node based on a delay control signal and generates firs... | 12/28/2004 |
| 6836166 | Method and system for delay control in synchronization circuits A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each... | 12/28/2004 |
| 6836163 | Differential output structure with reduced skew for a single input The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a s... | 12/28/2004 |
| 6831490 | Clock synchronization circuit and method A clock synchronization circuit for generating an output clock signal that is in synchronization with a reference clock signal and a method embodying the principle of operation of the circuit are disclosed. The circuit has a programmable delay element and a phase de... | 12/14/2004 |
| 6831492 | Common-bias and differential structure based DLL A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input re... | 12/14/2004 |
| 6829316 | Input circuit and output circuit An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on ... | 12/07/2004 |
| 6819153 | Semiconductor device for clock signals synchronization accuracy A semiconductor device that generates a clock which is synchronized with a reference signal stably and with fixed synchronization accuracy, and enables to deal with an abrupt variation in the reference signal. This semiconductor device includes N stages of delay ele... | 11/16/2004 |
| 6815990 | Delay locked loops having blocking circuits therein that enhance phase jitter immunity and methods of operating same DLL integrated circuits include least one delay element associated with the generation of an internal clock signal and a control circuit that is configured to periodically adjust a delay of said at least one delay element in response to a first clock signal (CLK). T... | 11/09/2004 |
| 6812799 | Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals A synchronous mirror delay includes a ring oscillator that generates a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal. In response to an input clock signal, a model delay line generates a model delayed clock sign... | 11/02/2004 |
| 6812760 | System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in respon... | 11/02/2004 |
| 6807243 | Delay clock generating apparatus and delay time measuring apparatus A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the dow... | 10/19/2004 |
| 6806750 | Method and system for clock deskewing using a continuously calibrated delay element in a phase-locked loop A method for clock deskewing using a continuously calibrated delay element in a phase-locked loop is provided that includes receiving a feedback signal. A skew select signal is received. The feedback signal is delayed based on the skew select signal to generate a de... | 10/19/2004 |
| 6801067 | Analog synchronous mirror delay circuit, method of generating a clock and internal clock generator using the same A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits, The ASMD circuit may include a comparator with first and second in... | 10/05/2004 |
| 6801070 | Measure-controlled circuit with frequency control A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path generates an internal signal based on the external signal. The delay locked circuit periodically performs... | 10/05/2004 |
| 6798258 | Apparatus and method for introducing signal delay A precision signal delay apparatus and method for introducing time delay to a signal. Precision delay is introduced by a pair of delay locked loops (DLLs) connected in series each with selected delay (i.e., a Vernier-type circuit). Nonuniformity in the precision del... | 09/28/2004 |
| 6794913 | Delay locked loop with digital to phase converter compensation A delay locked loop circuit 300 consistent with certain embodiments of the present invention has a delay line 304 with coarse adjustment 322 and fine adjustment 360 inputs. The coarse adjustment input 322 provides an overall adjust... | 09/21/2004 |
| 6795931 | Method and apparatus for an adjustable delay circuit having arranged serially coarse stages received by a fine delay stage A programmable delay circuit having a plurality of course delay stages (coupled in series fashion) and a fine delay stage having a plurality of parallel organized delay paths is described, wherein each of the parallel organized delay paths is adapted to receive inpu... | 09/21/2004 |
| 6794912 | Multi-phase clock transmission circuit and method A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for gene... | 09/21/2004 |
| 6791381 | Method and apparatus for reducing the lock time of a DLL A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay ele... | 09/14/2004 |
| 6784752 | Post-silicon phase offset control of phase locked loop input receiver A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedb... | 08/31/2004 |
| 6774689 | Triple input phase detector and methodology for setting delay between two sets of phase outputs An improved clock generation circuit using a multi-phase phase-locked loop (PLL) circuit design that incorporates a dual set of PLLs. A first PLL maintains frequency lock control of an oscillator while a second PLL controls various phase outputs from delay circuits ... | 08/10/2004 |
| 6774687 | Method and apparatus for characterizing a delay locked loop A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output ... | 08/10/2004 |
| 6775342 | Digital phase shifter After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the ... | 08/10/2004 |
