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| Number | Title | Issue Date |
| 8154330 | Delay line calibration mechanism and related multi-clock signal generator A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period ... | 04/10/2012 |
| 8143926 | Data signal generating apparatus It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. ... | 03/27/2012 |
| 8125258 | Phase synchronization device and phase synchronization method A sampling section (100A) includes a sampling filter (102) that converts a continuous-time signal into a discrete-time signal and applies filtering of low-pass characteristics and a one-bit quantizer (107) that outputs a quantized signal represe... | 02/28/2012 |
| RE43201 | DLL circuit and camcorder using DLL circuit A DLL circuit which can prevent transition to a pseudo lock state is provided. The DLL circuit includes a delay stage to which a reference clock is input and in which variable delay elements D able to change an amount of delay are connected in a plurality of stages,... | 02/21/2012 |
| 8098086 | Integrated circuit and programmable delay Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are... | 01/17/2012 |
| 8063682 | Semiconductor circuit for performing signal processing A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs pr... | 11/22/2011 |
| 8022741 | Digital electronic device and method of altering clock delays in a digital electronic device A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore compri... | 09/20/2011 |
| 8004329 | Hardware performance monitor (HPM) with variable resolution for adaptive voltage scaling (AVS) systems An apparatus includes a delay line having multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal through the delay cells. The apparatus also includes multiple sampling circuits configured to ... | 08/23/2011 |
| 7977988 | Delay adjusting method, and delay circuit A variable delay circuit 1 includes: a multistage delay circuit 20 constructed by connecting delay elements D1 to Dn in series; a selecting unit 21 which selects one delayed signal obtained by introducing different amounts of delay by pas... | 07/12/2011 |
| 7969216 | System and method for improved timing synchronization Embodiments of a method and system for both open-loop and closed-loop timing synchronization are provided in which a master clock signal, and a plurality of signals that define greater periods of time, are distributed to a plurality of host devices. A frame-sync sig... | 06/28/2011 |
| 7969215 | High-performance memory interface circuit architecture A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digita... | 06/28/2011 |
| 7956659 | Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control si... | 06/07/2011 |
| 7940100 | Delay circuits matching delays of synchronous circuits Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to... | 05/10/2011 |
| 7904859 | Method and apparatus for determining a phase relationship between asynchronous clock signals Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time, and sampli... | 03/08/2011 |
| 7893740 | Data signal generating apparatus A data signal generating apparatus with a data output unit for outputting m-bit parallel data and a data synchronization clock signal synchronized with the parallel data in response to a data request signal produced by dividing the frequency of a reference clock sig... | 02/22/2011 |
| 7893742 | Clock signal dividing circuit A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output ... | 02/22/2011 |
| 7893741 | Multiple-stage, signal edge alignment apparatus and methods Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions o... | 02/22/2011 |
| 7880519 | Clock signal generating circuit, display panel module, imaging device, and electronic equipment A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-fl... | 02/01/2011 |
| 7876140 | Signal adjusting system and signal adjusting method A signal adjusting system includes: a signal generating device for generating a plurality of output signals according to a plurality of pre-output signals, a plurality of signal transmitting paths being coupled to the signal generating device for transmitting the pl... | 01/25/2011 |
| 7741892 | Data output controller Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal an... | 06/22/2010 |
| 7728640 | DLL circuit A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each o... | 06/01/2010 |
| 7671651 | Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated i... | 03/02/2010 |
| 7652512 | Clock synchronizing circuit A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design... | 01/26/2010 |
| 7649391 | Clock signal transmission circuit A clock signal transmission circuit having a variable initial value for a wait time that is required until a clock signal stabilizes. The clock signal is generated from an original clock signal. The wait time setting unit generates a plurality of wait time signals t... | 01/19/2010 |
| 7639054 | Techniques for generating programmable delays A circuit includes a sensing circuit, a control circuit, and a programmable delay circuit. The sensing circuit generates delay compensation signals that change in response to variations in at least one of a process and a temperature of the circuit. The control circu... | 12/29/2009 |
| 7622971 | Delay locked loop circuits and methods of generating clock signals A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control voltage generator configured to output a control voltage based on the ... | 11/24/2009 |
| 7619454 | Clock generator for semiconductor memory apparatus The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first del... | 11/17/2009 |
| 7576580 | Energy efficient clock deskew systems and methods Systems and methods for active clock deskew are provided. The disclosed systems/methods advantageously achieve desirable clock deskew at reduced power levels by employing a resistance-based distributed clock deskew technique. The disclosed technique has broad commer... | 08/18/2009 |
| 7567104 | Data sampling clock edge placement training for high speed GPU-memory interface Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved data recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training ... | 07/28/2009 |
| 7535275 | High-performance memory interface circuit architecture A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digita... | 05/19/2009 |
| 7532051 | Method and apparatus for selection of an internal or external time delay A time delay circuit in a battery protection chip for an internal time delay or external time delay selection is disclosed. The protection chip has a selective pin for choosing the internal time delay while the selective pin is floated or the external time delay whi... | 05/12/2009 |
| 7525356 | Low-power, programmable multi-stage delay cell A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of t... | 04/28/2009 |
| 7514974 | Method and apparatus for adjusting on-chip delay with power supply control An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered ... | 04/07/2009 |
| 7495489 | Frequency multiplying delay-locked loop Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the inc... | 02/24/2009 |
| 7453297 | Method of and circuit for deskewing clock signals in an integrated circuit The methods and circuits of the various embodiments of the present invention relate to deskewing a generated clock signal. According to one embodiment, a method of deskewing a clock signal in a circuit having a delay line comprises steps of measuring an intrinsic de... | 11/18/2008 |
| 7446580 | System and method to improve the efficiency of synchronous mirror delays and delay locked loops A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay ... | 11/04/2008 |
| 7443216 | Trimmable delay locked loop circuitry with improved initialization characteristics Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay li... | 10/28/2008 |
| 7423462 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 09/09/2008 |
| 7423464 | Phase and amplitude modulator The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to an input signal, a first variable delay device having its input coupl... | 09/09/2008 |
| 7420430 | Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock sig... | 09/02/2008 |
