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| Number | Title | Issue Date |
| 7791385 | Spread spectrum clock generating apparatus A spread spectrum clock generating apparatus is disclosed. The spread spectrum clock generating apparatus includes a phase lock loop module and a spread spectrum module. The phase lock loop module is used for dynamically tuning frequency of an output clock. The spre... | 09/07/2010 |
| 7791386 | Externally synchronizing multiphase pulse width modulation signals Waveform errors between multiphase PWM signals caused by external synchronization signals is solved by providing a capture register in a master time base circuit. The capture register is triggered by the external sync signal so as to “capture” the value of the m... | 09/07/2010 |
| 7675335 | Phase detecting module and related phase detecting method A phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is arranged to compare a first input signal and a second input signal to generate a phase detecting result. The comparator is arranged to compare the phase... | 03/09/2010 |
| 7633324 | Data output strobe signal generating circuit and semiconductor memory apparatus having the same A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected cloc... | 12/15/2009 |
| 7548099 | Semiconductor device with delay section In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value w... | 06/16/2009 |
| 7489172 | DLL driver control circuit A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for gene... | 02/10/2009 |
| 7427883 | High bandwidth phase locked pool (PLL) A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses ... | 09/23/2008 |
| 7424083 | PLL noise smoothing using dual-modulus interleaving The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens” are not all counted consecutively. Instead, ones and tens are interle... | 09/09/2008 |
| 7398412 | Measure controlled delay with duty cycle control The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a dela... | 07/08/2008 |
| 7362155 | Method and apparatus for generating delays One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first clock signal and a third clock signal that is the inverse of the seco... | 04/22/2008 |
| 7358783 | Voltage, temperature, and process independent programmable phase shift for PLL A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability f... | 04/15/2008 |
| 7355922 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and ... | 04/08/2008 |
| 7348821 | Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable... | 03/25/2008 |
| 7349277 | Method and system for reducing the peak current in refreshing dynamic random access memory devices A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset co... | 03/25/2008 |
| 7339922 | System and method for synchronizing timers over wireless networks A method of synchronizing timers in a wireless network is described. According to some embodiments, a master timer is sampled at the start time of a first beacon in a first data object and the sampled master timer value is broadcast in a second beacon of a second da... | 03/04/2008 |
| 7339413 | Clock generator and organic light emitting display (OLED) including the clock generator A clock generator, which can be included in an Organic Light Emitting Display (OLED), includes four switching units and two inverters. Each of the switching units includes two transistors. Transistors of two switching units that are connected to a high-level voltage... | 03/04/2008 |
| 7336548 | Clock generating circuit with multiple modes of operation A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by... | 02/26/2008 |
| 7333390 | Phase controlled high speed interfaces A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circu... | 02/19/2008 |
| 7332948 | Duty cycle correction circuit of a DLL circuit The present invention relates to a duty cycle correction circuit of a DLL circuit. According to the present invention, in an Active Power-Down Mode (APDM), a voltage comparator of a duty cycle correction circuit operates without being reset. Therefore, although an i... | 02/19/2008 |
| 7323917 | Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase gene... | 01/29/2008 |
| 7321247 | Timer facility for high frequency processors with minimum dependency of processor frequency modes An apparatus, a method, and a computer program are provided for the generation of constant incremental increases while changing core clock frequencies. In computer systems, oftentimes frequency changes are useful. Maintaining the clocking ability of the computer sys... | 01/22/2008 |
| 7315597 | Sampling frequency conversion device and sampling frequency conversion method A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the sign... | 01/01/2008 |
| 7304523 | Clock generating apparatus and method in optical storage system A clock generating apparatus and clock generating method of an optical disc drive for calibrating a clock signal according to an input signal. The clock generating apparatus includes a frequency detector for detecting sampling times in a duration when the clock sign... | 12/04/2007 |
| 7295578 | Method and apparatus for synchronizing auxiliary data and video data transmitted over a TMDS-like link A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver a... | 11/13/2007 |
| 7292080 | Delay locked loop using a FIFO circuit to synchronize between blender and coarse delay control signals Embodiments of the present invention generally provide improved techniques and circuit configurations for a delay-locked loop (DLL) circuit. In one embodiment, a first phase difference between an input clock signal and an output clock signal is measured. Based on th... | 11/06/2007 |
| 7284145 | Clock control circuit and integrated circuit A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the targ... | 10/16/2007 |
| 7278015 | Methods and devices for DRAM initialization A device for DRAM initialization of a computer system. A detection circuit detects memory condition and outputs a fast initialization signal. A buffer stores initialization parameters of the memory. A memory controller sets the initialization parameters according to... | 10/02/2007 |
| 7274229 | Coarse tuning for fractional-N synthesizers An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tu... | 09/25/2007 |
| 7271664 | Phase locked loop circuit A phase locked loop circuit (PLL) has a reference terminal for receiving a reference signal and an output terminal for providing an output signal. The PLL comprises a phase comparator having first and second inputs and having an output at which it provides a signal ... | 09/18/2007 |
| 7272527 | Method of test of clock generation circuit in electronic device, and electronic device In an electronic device having an interface circuit which operates using a fast clock source, frequency deviation of the clock source is inspected in the mounted state. The clock pulses of the fast clock source are counted in synchronization with an electronic devic... | 09/18/2007 |
| 7259635 | Arbitrary frequency signal generator The present invention is based on the objective of constructing a PLL as arbitrary frequency generator for frequency multiplication purposes without utilizing a VCO. The invention shows a solution which can be realized with a pure digital circuit which can be easily... | 08/21/2007 |
| 7256630 | System and method for PLL control Systems and methods for reducing the effects of the operation of logic on a phase-locked loop (PLL) circuit are disclosed. These systems and methods may allow a PLL circuit to compensate for the anticipated effects of an instruction before, substantially simultaneou... | 08/14/2007 |
| 7256656 | All-digital phase-locked loop An all-digital phase-locked loop (ADPLL) includes: a digital phase frequency detector (PFD) for generating a detection signal by detecting frequency difference and phase difference between a reference signal and a feedback signal; a digital phase difference counter ... | 08/14/2007 |
| 7250803 | PLL output clock stabilization circuit A circuit includes: a PLL circuit which multiplies a reference clock by a multiplication factor and outputs a PLL clock; a first counter which counts up with the PLL clock for a fixed period of time; a comparator which compares a count value of the first counter wit... | 07/31/2007 |
| 7245540 | Controller for delay locked loop circuits A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external... | 07/17/2007 |
| 7242229 | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode A PLL circuit is described. The PLL circuit includes: a signal generator and at least one divider coupled to the signal generator, where the at least one divider is programmable in user mode. In one embodiment, the PLL circuit includes a memory device associated wit... | 07/10/2007 |
| 7233188 | Methods and apparatus for reducing power consumption in a processor using clock signal control Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a subst... | 06/19/2007 |
| 7228515 | Methods and apparatuses for validating AC I/O loopback tests using delay modeling in RTL simulation Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate ana... | 06/05/2007 |
| 7215181 | High voltage generator circuit with ripple stabilization function The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage... | 05/08/2007 |
| 7212053 | Measure-initialized delay locked loop with live measurement A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or otherwise determined, while continuing to produce the first output signal. Thereafter, a second output signa... | 05/01/2007 |
