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| Number | Title | Issue Date |
| 8154329 | Device and method for phase compensation A frequency generation unit is provided that permits a receiver to tune from channel to channel without cycle skipping and in which compensation for phase offset introduced during tuning is provided. The frequency generation unit includes a fractional-N synthesizer,... | 04/10/2012 |
| 8149035 | Multi-output PLL output shift Controlling a PLL includes providing a voltage controlled oscillator (VCO) and coupling an output of the VCO to a shifter circuit. The shifter circuit has a shifter circuit output, the shifter circuit also including an activation input for receiving an activation si... | 04/03/2012 |
| 8120400 | Phase locked loop circuit A Phase Locked Loop circuit, includes: a main path through which an input signal is propagated, and an actual signal is output; a main feedback path through which the actual signal is fed back to an input stage of the main path; and a local feedback path through whi... | 02/21/2012 |
| 8085075 | Method and system for diagnostic imaging using a digital phase locked loop A method and apparatus are provided for minimizing output pulse jitters in a phase locked loop. The method includes pre-setting the digital phase locked loop to a desired frequency, locking the digital phase locked loop to the desired frequency to generate an output... | 12/27/2011 |
| 8018259 | Phase-locked loop having a feedback clock detector circuit and method therefor A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control v... | 09/13/2011 |
| 7999586 | Digital phase locked loop with closed loop linearization technique Apparatuses, systems, and a method for providing a digital phase-locked loop (PLL) are described. In one embodiment, an apparatus includes an integration-mode phase frequency detector (PFD) that compares a phase and frequency of a reference clock signal to a phase a... | 08/16/2011 |
| 7973579 | Device and method for phase synchronization with the aid of a microcontroller A phase controller device according to the invention comprises a hardware core that is formed by a signal detector, a voltage-controlled oscillator, a phase comparator, and an integration unit, where the hardware core, by controlling the working clock pulse frequenc... | 07/05/2011 |
| 7956658 | Digital lock detector and frequency synthesizer using the same There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits;... | 06/07/2011 |
| 7948290 | Digital PLL device An input clock dividing unit frequency-divides an input clock, and an input clock multiplying unit frequency-multiplies the input clock. An operation clock selecting unit selects the frequency-divided clock when the input clock is fast and selects the frequency-mult... | 05/24/2011 |
| 7944261 | Method and apparatus for detecting clock loss Method and apparatus for detecting clock loss in clock circuit. An example of the invention relates to detecting loss of a feedback clock signal input to a digital clock manager, where the feedback clock signal is derived from the reference clock signal. A clock div... | 05/17/2011 |
| 7940099 | Method of improving noise characteristics of an ADPLL and a relative ADPLL An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The ... | 05/10/2011 |
| 7932760 | System and method for implementing a digital phase-locked loop An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count dow... | 04/26/2011 |
| 7924076 | Data recovery circuit Provided is a data recovery circuit including an input data phase detection circuit for outputting a gate signal synchronized with a rising phase of input data, a gated multiphase oscillator for instantly generating N-phase clocks based on the gate signal as a trigg... | 04/12/2011 |
| 7915935 | Communication systems w/counter-based frequency centering for mm-wave frequency bands A low-cost and power-efficient communication system using digital frequency centering techniques suitable for millimeter-wave wide-bandwidth bands with mostly digital components. Significant circuitry in the frequency source can be switched-off, thus conserving powe... | 03/29/2011 |
| 7911248 | Apparatus for linearization of digitally controlled oscillator There is provided an apparatus for the linearization of a digitally controlled oscillator. The apparatus includes a first filter outputting only a low frequency band signal of an input signal to the digitally controlled oscillator; a negative feedback loop causing t... | 03/22/2011 |
| 7772900 | Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to f... | 08/10/2010 |
| 7759993 | Accumulated phase-to-digital conversion in digital phase locked loops Techniques for converting an accumulated phase of a signal into a digital value in a digital phase-locked loop (DPLL). In an exemplary embodiment, a signal is coupled to a divide-by-N module that divides the frequency of the signal down by a divider ratio N. The div... | 07/20/2010 |
| 7750701 | Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analo... | 07/06/2010 |
| 7683685 | System and method for implementing a digital phase-locked loop An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count dow... | 03/23/2010 |
| 7656208 | PLL oscillation circuit A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation ... | 02/02/2010 |
| 7646227 | Digital phase discriminator A phase discriminator for being used in a phase-locked loop to determine if a phase difference between a reference signal and a target signal has reached a programmable gap value is disclose which comprises a programmable phase gap selector receiving the reference s... | 01/12/2010 |
| 7495488 | Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same A phase-locked loop (PLL) circuit includes a phase/frequency detector (PFD), a charge pump, a loop filter, a control circuit, a VCO, and a feedback circuit. The control circuit generates a digital control signal in response to the up signal, the down signal, and the... | 02/24/2009 |
| 7439812 | Auto-ranging phase-locked loop A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit. The rangefinder circuit is configured to control the dividing factor in... | 10/21/2008 |
| 7423463 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 09/09/2008 |
| 7421048 | System and method for multimedia delivery in a wireless environment A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing ... | 09/02/2008 |
| 7420426 | Frequency modulated output clock from a digital phase locked loop A frequency modulated output of a digital locked loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequen... | 09/02/2008 |
| 7414448 | Duty cycle correction circuit A duty cycle correction circuit comprises a tuned circuit, a delay circuit and a phase-locked loop; wherein the tuned circuit receives an input clock, generates a periodic pulse according to the input clock, tunes the periodic pulse depending on a reference voltage,... | 08/19/2008 |
| 7402821 | Application of digital frequency and phase synthesis for control of electrode voltage phase in a high-energy ion implantation machine, and a means for accurate calibration of electrode voltage phase An improved HE LINAC-based ion implantation system is disclosed utilizing direct digital synthesis (DDS) techniques to obtain precise frequency and phase control and automated electrode voltage phase calibration. The DDS controller may be used on a multi-stage linea... | 07/22/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7391839 | Accumulator based phase locked loop There is disclosed a phase locked loop comprising: a phase frequency detector for receiving as a first input a reference signal and for generating a control signal; a voltage controlled oscillator for receiving the control signal and for generating a signal defining... | 06/24/2008 |
| 7388415 | Delay locked loop with a function for implementing locking operation periodically during power down mode and locking operation method of the same A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock generator, a clock delay unit, and a power down control unit. The power down ... | 06/17/2008 |
| 7386084 | Method and system for pattern-independent phase adjustment in a clock and data recovery (CDR) circuit Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage through a first variable resistor. A single output reference XOR gate may be coupled to a latched differe... | 06/10/2008 |
| 7382678 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 06/03/2008 |
| 7375562 | Phase locked system for generating distributed clocks A PLL apparatus and system for generating distributed clocks are disclosed. A synchronizing-edge detector is provided to the PLL apparatus in the PLL system to detect synchronizing edges of the input and output clock signals having gear relationship for the PLL appa... | 05/20/2008 |
| 7375557 | Phase-locked loop and method thereof and a phase-frequency detector and method thereof The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a del... | 05/20/2008 |
| 7372341 | Noise immunity circuitry for phase locked loops and delay locked loops A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the re... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7368963 | Delay locked loop for use in semiconductor memory device and method thereof A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locke... | 05/06/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7368964 | Delay locked loop in semiconductor memory device and method for generating divided clock therein Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clo... | 05/06/2008 |
