Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8183901 | Delay locked loop circuit and method Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference... | 05/22/2012 |
| 8179177 | Wideband delay-locked loop (DLL) circuit A wideband delay-locked loop (DLL) circuit includes an internal clock signal generating unit providing an internal control signal by selecting and interpolating between two clock delay signals during a primary phase locking operation. The internal clock signal may b... | 05/15/2012 |
| 8174298 | Method and apparatus for improving accuracy of signals delay A delay module, includes a first delay unit, a second delay unit and an inverter. Each of the first and second delay units includes: a logic gate for gating and a logic gate for delaying. The input port of the logic gate for gating of the first delay unit is electri... | 05/08/2012 |
| 8169243 | Techniques for non-overlapping clock generation Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in tu... | 05/01/2012 |
| 8164372 | Semiconductor device having level shift circuit, control method thereof, and data processing system To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first inte... | 04/24/2012 |
| 8164369 | Techniques for minimizing control voltage noise due to charge pump leakage in phase locked loop circuits Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a ... | 04/24/2012 |
| 8164370 | Clock control circuit and semiconductor device including the same A clock control circuit includes a phase determination circuit that generates a first phase determination signal based on a phase of an external clock signal, a counter circuit that updates a count value based on a second phase determination signal for each sampling... | 04/24/2012 |
| 8164371 | Duty detection circuit, clock generation circuit including the duty detection circuit, and semiconductor device To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another... | 04/24/2012 |
| 8164368 | Power savings mode for memory systems A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in ... | 04/24/2012 |
| 8159276 | Method for using digital PLL in a voltage regulator A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop. ... | 04/17/2012 |
| 8159277 | Techniques for providing multiple delay paths in a delay circuit A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuit... | 04/17/2012 |
| 8154328 | Techniques for measuring phases of periodic signals A phase detector circuit generates a phase comparison signal based on a phase difference between first and second periodic signals during a test mode. Phases of the first and the second periodic signals do not change in response to variations in a signal generated b... | 04/10/2012 |
| 8149033 | Phase control device, phase-control printed board, and control method A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compar... | 04/03/2012 |
| 8149034 | Delay lines, methods for delaying a signal, and delay lock loops Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected... | 04/03/2012 |
| 8143925 | Delay locked loop A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica de... | 03/27/2012 |
| 8138808 | Circuit for detecting phase imbalance of signals A circuit for detecting a phase imbalance of signals includes a conversion block and a comparator coupled to the conversion block. The conversion block generates generating a direct current (DC) signal based on a first signal and a second signal. The level of the DC... | 03/20/2012 |
| 8138809 | Periodic signal delay apparatus, systems, and methods Apparatus, systems, and methods are disclosed that operate to delay a periodic input signal in one or more delay elements of a group of delay elements to generate a periodic output signal and to vary a power supply to the delay elements. Additional apparatus, system... | 03/20/2012 |
| 8130016 | Techniques for providing reduced duty cycle distortion A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuit... | 03/06/2012 |
| 8130017 | Semiconductor device having a delay locked loop responsive to skew information and method for driving the same A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generat... | 03/06/2012 |
| 8125257 | Apparatus and method for modeling coarse stepsize delay element and delay locked loop using same A reference circuit and method for mitigating switching jitter and delay-locked loop (DLL) using same are provided. The reference circuit and method determine a number of steps of a fine delay line (FDL) that are equivalent to a step of a coarse delay line (CDL). Sw... | 02/28/2012 |
| 8120396 | Delay locked loop circuit A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by compa... | 02/21/2012 |
| 8120397 | Delay locked loop apparatus A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector ... | 02/21/2012 |
| 8120398 | Delay locked loop circuit A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and... | 02/21/2012 |
| 8120399 | Locked loop circuit with clock hold function A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and th... | 02/21/2012 |
| 8115528 | Method and apparatus for output data synchronization with system clock A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to delay an external clock signal to produce a substantially in-phase output clock signal, a main loop configu... | 02/14/2012 |
| 8106692 | Method for tracking delay locked loop clock A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, ... | 01/31/2012 |
| 8106693 | Delay locked loop circuit and operation method thereof A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a t... | 01/31/2012 |
| 8106694 | DLL circuit A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle ... | 01/31/2012 |
| 8093934 | Timing adjustment circuit, solid-state image pickup element, and camera system A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a ... | 01/10/2012 |
| 8089308 | Phase controlling apparatus, phase-control printed board, and controlling method In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a... | 01/03/2012 |
| 8085072 | Semiconductor integrated circuit having delay locked loop circuit A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a ... | 12/27/2011 |
| 8085074 | Fast-locking delay locked loop A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sam... | 12/27/2011 |
| 8085073 | Phase synchronization apparatus A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corr... | 12/27/2011 |
| 8081021 | Delay locked loop A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount... | 12/20/2011 |
| 8076963 | Delay-locked loop having a delay independent of input signal duty cycle variation A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capa... | 12/13/2011 |
| 8072248 | Method and apparatus for improving accuracy of signals delay A delay module, a delay method, a clock detection apparatus, and a digital locked loop (DLL) are disclosed. The delay module includes a first delay unit, a second delay unit and an inverter. Each of the first delay unit and the second delay unit include two logic ga... | 12/06/2011 |
| 8072249 | Clock jitter compensated clock circuits and methods for generating jitter compensated clock signals Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship rel... | 12/06/2011 |
| 8067967 | Phase delay line A phase delay line comprises a phase-locked loop, a duty-cycle adjusting ring and a voltage-sharing to time-sharing converter, wherein the phase-locked loop and the duty-cycle adjusting ring form a loop, and one output of the phase-locked loop is connected with the ... | 11/29/2011 |
| 8067968 | Locking state detector and DLL circuit having the same A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference d... | 11/29/2011 |
| 8067966 | Voltage controlled delay loop and method with injection point control A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of del... | 11/29/2011 |
