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| Number | Title | Issue Date |
| 7320082 | Power control system for synchronous memory device A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is ove... | 01/15/2008 |
| 7319728 | Delay locked loop with frequency control A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry f... | 01/15/2008 |
| 7319351 | Delay generator with symmetric signal paths A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time... | 01/15/2008 |
| 7319462 | Display apparatus, driving method, and projection apparatus In a display apparatus in accordance with the present invention, (i) a sampling circuit for sampling video signals supplied via a plurality of video lines and (ii) connecting lines for connecting the video lines with respective analog switch groups in the sampling c... | 01/15/2008 |
| 7320049 | Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode ... | 01/15/2008 |
| 7319350 | Lock-detection circuit and PLL circuit using same A lock-detection circuit that can set an acceptable phase-error range adapted to define a locked state and/or an unlocked state at a constant rate without being affected by a frequency and that can detect the locked state and/or the unlocked state with precision wit... | 01/15/2008 |
| 7319352 | Phase and amplitude modulator The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to an input signal, a first variable delay device having its input coupl... | 01/15/2008 |
| 7317345 | Anti-gate leakage programmable capacitor An anti-gate leakage programmable capacitor including at least one capacitor having a first terminal coupled to a first node and a second terminal, a second node, and a control circuit which selectively couples the second terminal of the capacitor to the second node... | 01/08/2008 |
| 7317342 | Clock distribution network using feedback for skew compensation and jitter filtering A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering. In an embodiment, a number of clock processor nodes are distributed throughout the clock distribution network on the ... | 01/08/2008 |
| 7317775 | Switched deskew on arbitrary data A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first samplin... | 01/08/2008 |
| 7317359 | Circuits and methods for phase locked loop lock window detection Circuits and methods for detecting the lock status of a phase locked loop (PLL). The circuit generally comprises (a) a controller configured to produce a control signal in response to a reference clock signal, (b) a counter configured to count pulses of an output si... | 01/08/2008 |
| 7317362 | Oscillator circuit and oscillation control method An oscillator circuit is disclosed that includes a first oscillation part configured to output a first oscillation output by charging and discharging a first capacitor, and a second oscillation part configured to output a second oscillation output by charging and di... | 01/08/2008 |
| 7315596 | Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at mul... | 01/01/2008 |
| 7315217 | Linear phase-locked loop with dual tuning elements A linear PLL includes a VCO with first and second tuning elements. The first tuning element is adjusted in proportion to the phase error between an input signal and a VCO signal and the second tuning element is adjusted by an integral function of the phase error. By... | 01/01/2008 |
| 7315189 | Retiming circuits for phase-locked loops Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sa... | 01/01/2008 |
| 7315601 | Low-noise sigma-delta frequency synthesizer A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a... | 01/01/2008 |
| 7312666 | PLL circuit configured to distribute its loop control signal to CDR circuits A semiconductor integrated circuit includes a phase-locked loop (PLL) circuit configured to generate an oscillation output signal synchronized with a reference clock and a plurality of clock and data recovery (CDR) circuits configured to adjust a phase of the oscill... | 12/25/2007 |
| 7312668 | High resolution PWM generator or digitally controlled oscillator A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal through a series of delays, all of which are controlled by a delay l... | 12/25/2007 |
| 7312667 | Statically controlled clock source generator for VCDL clock phase trimming The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock sour... | 12/25/2007 |
| 7312642 | Continuous, wide-range frequency synthesis and phase tracking methods and apparatus Circuitry and methods are provided for continuously adjustable frequency synthesis. The synthesis covers a wide range of possible frequencies and can be performed to a high degree of precision. In an embodiment of the invention, an analog phase-locked loop (“PLL... | 12/25/2007 |
| 7313178 | Transceiver for receiving and transmitting data over a network and method for testing the same The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, ... | 12/25/2007 |
| 7312663 | Phase-locked loop having a bandwidth related to its input frequency An integrated circuit includes a phase-locked loop (PLL) in which the loop bandwidth of the PLL is proportional to the input frequency of the PLL. The PLL includes a phase/frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (V... | 12/25/2007 |
| 7310009 | Phase locked loop circuit having deadlock protection circuit and methods of operating same A phase locked loop (PLL) circuit having a deadlock protection circuit and a deadlock protection method of the PLL circuit are provided. The PLL circuit includes: a phase frequency detector, which receives an input clock signal and a divided clock signal and compare... | 12/18/2007 |
| 7310010 | Duty cycle corrector A duty cycle corrector includes a first controllable delay, a second controllable delay, a phase detector, and a compensation circuit. The first controllable delay is configured to delay a first signal to provide a second signal. The second controllable delay is con... | 12/18/2007 |
| 7310401 | Programmable frequency detector for use with a phase-locked loop A frequency detector for use with a PLL utilizes a counter and a preset value to produce frequency information related to a VCO signal. The frequency information is used to control the frequency of the VCO signal and to determine whether the VCO signal should be con... | 12/18/2007 |
| 7307459 | Programmable phase-locked loop circuitry for programmable logic device A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections... | 12/11/2007 |
| 7304516 | Method and apparatus for digital phase generation for high frequency clock applications An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal.... | 12/04/2007 |
| 7304923 | Disk drive and detection method using pre-pit detection and push-pull signal generation A push pull signal is detected from a disk-shaped storage medium on which wobbling grooves are formed as recording tracks and address information is recorded by forming pre-pits on lands between adjacent grooves. The detected push-pull signal is compared with a refe... | 12/04/2007 |
| 7304545 | High latency timing circuit A phase locked loop (PLL) circuit, comprises a frequency integrator circuit that receives a target signal, a phase shift signal and a frequency gain correction parameter and that selectively disables tracking frequency offset based on a value of the frequency gain c... | 12/04/2007 |
| 7304515 | Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay apparatus with variably controllable delay period, in which a clock pulse or a signal derived from it, has a v... | 12/04/2007 |
| 7301415 | Automatic frequency tuning in a phase lock loop A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interp... | 11/27/2007 |
| 7301413 | Voltage controlled oscillator and PLL circuit A voltage comparing circuit activates a first voltage comparison signal when a control voltage is lower than a first reference voltage and a second voltage comparison signal when the control voltage is higher than a second reference voltage. In synchronization with ... | 11/27/2007 |
| 7301404 | Method and apparatus for transceiver frequency synthesis A method and apparatus for frequency synthesis in a transceiver are based on providing a primary frequency synthesizer configured to synthesize a receiver frequency signal from a receiver reference frequency signal, and providing an offset frequency synthesizer conf... | 11/27/2007 |
| 7301405 | Phase locked loop circuit The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulate... | 11/27/2007 |
| 7298218 | Frequency synthesizer architecture A frequency synthesizer is provided with a PLL, including a divider by N circuit and a phase generation circuit which is connected to the output of the VCO of the PLL. The phase generation circuit generates a predetermined number of phases synchronized on the freque... | 11/20/2007 |
| 7298191 | Reset-free delay-locked loop A delay locked loop (DLL) includes a delay unit configured to delay an input clock signal by a specified amount to produce a delayed clock signal. A phase detector receives as input the input clock signal and the delayed clock signal and outputs a signal proportiona... | 11/20/2007 |
| 7295048 | Method and apparatus for generating spread spectrum clock signals having harmonic emission suppressions A method for generating spread spectrum clock signals having harmonic emission suppressions is disclosed. A set of delayed clock signals is initially generated by delaying a high-speed clock signal via a set of delay modules. Then, the leading edge of a first one of... | 11/13/2007 |
| 7295049 | Method and circuit for rapid alignment of signals Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of ... | 11/13/2007 |
| 7295643 | Method and a device for phase and frequency comparison The phase and frequency comparator for controlling, as a function of the frequency (Fref) and the phase of a reference signal (Sref), the frequency (Fvco) and the phase of the output signal of a controlled-frequency oscillator compri... | 11/13/2007 |
| 7296173 | Semiconductor integrated circuit A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input te... | 11/13/2007 |
