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| Number | Title | Issue Date |
| 7501866 | Delay locked loop circuit A synchronous memory device having a normal mode and a power down mode includes a power down mode controller for generating a power down mode control signal in response to a clock enable signal, thereby determining onset or termination of a power down mode. A clock ... | 03/10/2009 |
| 7498856 | Fractional-N frequency synthesizer A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic ... | 03/03/2009 |
| 7492194 | Oscillator including phase frequency detectors for detecting a phase difference between two input signals and outputting a control command signal An oscillator includes phase frequency detectors, each detecting the phase difference between two input signals (output signal and external reference signal) and outputting a control command signal for controlling the output signal to achieve a desired frequency on ... | 02/17/2009 |
| 7492195 | Agile, low phase noise clock synthesizer and jitter attenuator A phase locked loop circuit, system, and method of operation are provided. The phase-locked loop (PLL) includes a first PLL and a second PLL. The first PLL is nested inside the second PLL. According to one embodiment, the first PLL is coupled to the output of a surf... | 02/17/2009 |
| 7486118 | Signal generating apparatus and method thereof A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signa... | 02/03/2009 |
| 7479815 | PLL with dual edge sensitivity A divider apparatus for use within a phase-locked loop having an output terminal at which an output frequency is produced. The apparatus includes a prescalar circuit configured to produce a prescaled signal by dividing the output frequency in response to a mode sele... | 01/20/2009 |
| 7479814 | Circuit for digital frequency synthesis in an integrated circuit A circuit for frequency synthesis in an integrated circuit is described. The circuit comprises an oscillator circuit having a counter-controlled delay line. A delay register is coupled to the counter-controlled delay line. The delay register stores a delay value for... | 01/20/2009 |
| 7471126 | Phase locked loop utilizing frequency folding A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and ... | 12/30/2008 |
| 7466175 | Capacitance multiplier circuit An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacit... | 12/16/2008 |
| 7466174 | Fast lock scheme for phase locked loops and delay locked loops A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signa... | 12/16/2008 |
| 7449927 | Delay locked loop circuit A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a sec... | 11/11/2008 |
| 7449928 | Semiconductor device According to the present invention, there is provided a semiconductor device including: a phase locked loop circuit having, a phase frequency detector which receives a reference signal and a frequency-divided signal, and outputs a phase difference detection signal b... | 11/11/2008 |
| 7446578 | Spread spectrum clock generator A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. ... | 11/04/2008 |
| 7443247 | Circuit arrangement for detection of a locking condition for a phase locked loop, and a method A circuit arrangement includes a phase locked loop, having a phase detector on whose output side a phase signal can be tapped off and whose output side is coupled to a charge pump. Furthermore, the phase locked loop includes an oscillator whose input side is coupled... | 10/28/2008 |
| 7443215 | Methods and apparatus to increase the resolution of a clock synthesis circuit that uses feedback interpolation A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. ... | 10/28/2008 |
| 7443761 | Loop filtering for fast PLL locking Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL) path while applying a control voltage of the DLL path to a loop filter of the DLL path. The method includes... | 10/28/2008 |
| 7443213 | Staged locking of two phase locked loops Data synchronization is achieved in devices which transmit and/or receive audio and/or video data through the staged locking of phase locked loops. According to an exemplary embodiment, a transmitter includes a serial data source. An encoder provides encoded data an... | 10/28/2008 |
| 7443214 | PLL circuit and frequency setting circuit using the same Disclosed is a PLL circuit in which an AC signal with a predetermined frequency is supplied as an input signal to a phase shifter comprising an OTA and a capacitor, and a phase comparator that receives the input signal to the phase shifter and an output signal from ... | 10/28/2008 |
| 7440518 | Phase-locked loop circuit A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (uDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a ... | 10/21/2008 |
| 7436231 | Low power and low timing jitter phase-lock loop and method A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. Th... | 10/14/2008 |
| 7436229 | Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. ... | 10/14/2008 |
| 7432749 | Circuit and method for improving frequency range in a phase locked loop A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a... | 10/07/2008 |
| 7432751 | High performance signal generation A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal ... | 10/07/2008 |
| 7432769 | Oscillator circuit The oscillating unit 11 generates a signal having a frequency of n*f, i.e., n times a target frequency f. The control voltage generation circuit 21 compares the phase difference between a divided signal of a signal generated in the oscillating unit ... | 10/07/2008 |
| 7432750 | Methods and apparatus for frequency synthesis with feedback interpolation A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. ... | 10/07/2008 |
| 7430680 | System and method to align clock signals A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers... | 09/30/2008 |
| 7429874 | Replica bias circuit Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors ... | 09/30/2008 |
| 7427883 | High bandwidth phase locked pool (PLL) A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses ... | 09/23/2008 |
| 7427899 | Apparatus and method for operating a variable segment oscillator This disclosure is directed to a communications device having a comparator that receives a signal associated with an output and produces a signal associated with a difference between a reference signal and the output signal. A loop filter is coupled to the comparato... | 09/23/2008 |
| 7425852 | Phase-locked loop The present invention relates to a phase-locked loop for frequency synthesis, which has a memory for a control value for the controllable oscillator of the phase-locked loop, which is connectable via a first switch to the control input of the controllable oscillator... | 09/16/2008 |
| 7425851 | Phase-locked loop with incremental phase detectors and a converter for combining a logical operation with a digital to analog conversion The invention relates to a phase-locked loop comprising a voltage controlled oscillator and having a frequency control input for controlling the frequency of the output signal. The phase-locked loop also has a phase comparator for deriving a control signal from a ph... | 09/16/2008 |
| 7421048 | System and method for multimedia delivery in a wireless environment A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing ... | 09/02/2008 |
| 7421053 | Fast clock acquisition enable method using phase stir injection to PLL for burst mode optical receivers Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to loc... | 09/02/2008 |
| 7420870 | Phase locked loop circuit and method of locking a phase A phase locked loop circuit and method of locking a phase. The phased locked loop circuit may include a phase detector receiving an external clock signal and a feedback clock signal and outputting an up signal when a phase of the external clock signal leads a phase ... | 09/02/2008 |
| 7420426 | Frequency modulated output clock from a digital phase locked loop A frequency modulated output of a digital locked loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequen... | 09/02/2008 |
| 7417477 | PLL circuit To a frequency divider having a reset function, a second clock of a frequency N×Y times higher than that of a first clock is inputted. Upon receipt of a signal indicating that the stop of the input clock is detected by a start/stop detection circuit, the frequency ... | 08/26/2008 |
| 7417510 | Direct digital interpolative synthesis A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value cor... | 08/26/2008 |
| 7415092 | Low wander timing generation and recovery Systems, apparatuses, and methods for low wander timing generation and/or recovery are disclosed here. In one aspect, embodiments of the present disclosure include a communication system for high speed communications between a first location and a second location. T... | 08/19/2008 |
| 7411461 | Frequency and/or phase lock loops with beat frequency estimation A control loop (10) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference (11) and oscillator (25) output signals, a beat frequency generator (12) for producing a signal... | 08/12/2008 |
| 7412019 | Spread spectrum clock generator A spread spectrum clock generator comprising a phase-locked loop circuit and a modulation circuit. The phase-locked loop circuit receives a reference signal at a reference frequency and outputs an output signal at an output frequency periodically varying in a range ... | 08/12/2008 |
