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Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 7271633 | Charge pump structure for reducing capacitance in loop filter of a phase locked loop A charge pump and loop filter circuit of a phase locked loop includes a resistor, first and second capacitors, first and second input current sources for supplying first and second currents to the circuit, a first output current source for outputting the first curre... | 09/18/2007 |
| 7272742 | Method and apparatus for improving output skew for synchronous integrated circuits A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffer... | 09/18/2007 |
| 7271631 | Clock multiplication circuit A clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The circuit delivers an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as i... | 09/18/2007 |
| 7268599 | Method and apparatus for buffer with programmable skew A method and apparatus for a buffer with programmable skew have been disclosed. Several output signals are generated. Based on one of the output signals several feedback signals are generated. The feedback signals are then received and compared. Based on the compari... | 09/11/2007 |
| 7269094 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 09/11/2007 |
| 7269217 | PWM controller with integrated PLL A pulse-width modulation (PWM) controller to supply power to electronic components using a phase lock loop (PLL) is presented. A PWM controller comprises an input node operable to receive a reference signal and a phase-locked loop (PLL). The PLL comprises an oscilla... | 09/11/2007 |
| 7268629 | System and method for lock detection of a phase-locked loop circuit Systems and methods for detecting phase-locked loop circuit lock. In particular, a lock detector configured to detect PLL stability for a user-defined period of time prior to asserting a PLL-lock-detected output. Stability may be indicated by a counter inserted into... | 09/11/2007 |
| 7268631 | Phase locked loop with scaled damping capacitor In order to reduce the area of a charge pump PLL, one may separate proportional component and integral component of the loop filter voltage, and add additional circuitry so as to make the integral component appear as though it is affected by a much larger value of c... | 09/11/2007 |
| 7268600 | Phase- or frequency-locked loop circuit having a glitch detector for detecting triggering-edge-type glitches in a noisy signal A phase- or frequency-locked loop circuit (200) that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches (148, 304A, 304B) in the input reference clock signal (REF_CLK). The locked-loop circuit... | 09/11/2007 |
| 7268825 | Digital synchronizing generator A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A nume... | 09/11/2007 |
| 7265588 | Dynamic clock change circuit A clock change circuit includes enabling a clock change frequency to be accepted while a system is active and clock frequencies are at a low period. The circuit includes generating an enabling signal representing a window of time in which a frequency change is accom... | 09/04/2007 |
| 7265625 | Amplifier systems with low-noise, constant-transconductance bias generators Amplifier systems are provided with bias generators that substantially stabilize operating points of system parameters (e.g., drain current and transconductance) over PVT variations, substantially reduce body effects and Early effects, and substantially reduce syste... | 09/04/2007 |
| 7265635 | Method and apparatus for assisting pull-in of a phase-locked loop A method, algorithm, software, architecture, circuit, and/or system for assisting pull-in of a phase-locked loop (PLL) are disclosed. In one embodiment, a PLL can include: (i) a phase detector that may receive a serial data stream and output a pump control signal; (... | 09/04/2007 |
| 7266172 | Fully differential CMOS phase-locked loop The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C3MO... | 09/04/2007 |
| 7266170 | Signal generating circuit, timing recovery PLL, signal generating system and signal generating method A control signal that runs a control oscillator of a signal generation circuit that generates a write clock is taken as a reference signal. That reference signal is supplied to a signal generation circuit that generates a read clock. In the signal generation circuit... | 09/04/2007 |
| 7265636 | Method of correcting the phase difference between two input signals of a phase-locked loop and associated device A method for correcting the phase difference between two input signals of a phase-locked loop may include a charge pump connected to a filter. Prior to the occurrence of the first of the two input signals, a calibration phase may be carried out in which the input of... | 09/04/2007 |
| 7265637 | Startup/yank circuit for self-biased phase-locked loops An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, ... | 09/04/2007 |
| 7266171 | Phase-locked loop circuit and radio communication apparatus using the same A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency and includes a current output type phase comparator which converts a phase differenc... | 09/04/2007 |
| 7266062 | Noise removal using 180-degree or 360-degree phase shifting circuit A noise removal circuit of the present invention comprises a 180-degree odd multiple shifting section for outputting a 180-degree shifted signal that is phase-shifted from an input signal by an odd multiple of 180 degrees and difference output section for outputting... | 09/04/2007 |
| 7266474 | Ring oscillator structure and method of separating random and systematic tolerance values A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to differe... | 09/04/2007 |
| RE39807 | Phase locked loop circuit A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data p... | 09/04/2007 |
| 7263628 | Method and apparatus for receiver circuit tuning A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an a... | 08/28/2007 |
| 7263152 | Phase-locked loop structures with enhanced signal stability Phase-locked loop structures are provided that facilitate enhanced stability of loop-generated signals. They include an oscillator network, a feedback loop and a controller. The oscillator network generates a loop output signal with a frequency that varies in respon... | 08/28/2007 |
| 7263154 | Method and apparatus for enabling fast clock phase locking in a phase-locked loop In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the p... | 08/28/2007 |
| 7262647 | Delay locked loop circuit and signal delay locking method A delay locked loop circuit and signal delay locking method are provided. First, the start-up circuit minimizes the delay time between an output signal and a reference signal during an initial period. Secondly, the phase correction circuit increases the delay time d... | 08/28/2007 |
| 7262645 | System and method for adjusting the phase of a frequency-locked clock A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the syst... | 08/28/2007 |
| 7262624 | Bi-directional buffer for interfacing test system channel An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the... | 08/28/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7259600 | Scalable integrated circuit architecture An integrated circuit architecture comprises a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) generates an output signal to an input of the feedback circuit. A master transistor ... | 08/21/2007 |
| 7259633 | Frequency synthesizer with loop filter calibration for bandwidth control According to one exemplary embodiment, a frequency synthesizer module includes a loop filter, where the loop filter includes a capacitor having a first terminal and a second terminal. The frequency synthesizer module further includes a loop filter calibration module... | 08/21/2007 |
| 7260168 | Network measurement method and apparatus The apparatus measures timing variations, such as the jitter or wander in a timing signal (100) of a telecommunications network. A recovered clock signal is sampled and digitized to produce a series of digital clock samples which are then processed (135 | 08/21/2007 |
| 7256656 | All-digital phase-locked loop An all-digital phase-locked loop (ADPLL) includes: a digital phase frequency detector (PFD) for generating a detection signal by detecting frequency difference and phase difference between a reference signal and a feedback signal; a digital phase difference counter ... | 08/14/2007 |
| 7256631 | Charge pump with balanced and constant up and down currents A charge pump generates a first sub up current and a second sub up current that vary complementarily with a change in a voltage at an output terminal. The charge pump also generates a first sub down current and a second sub down current that vary complementarily wit... | 08/14/2007 |
| 7256627 | Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for out... | 08/14/2007 |
| 7256629 | Phase-locked loops A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module fu... | 08/14/2007 |
| 7257176 | Method of frequency and phase offset estimation using least square method in a burst receiver A method provides frequency and phase offset estimation in a SCDMA burst receiver (such as a DOCSIS 2.0 SCDMA burst receiver) by application of the known Least Square (LS) parameter estimation algorithm to a pre-known transmitted sequence, called preamble, in order ... | 08/14/2007 |
| 7256628 | Speed-matching control method and circuit One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an extern... | 08/14/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7253674 | Output clock phase-alignment circuit A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are dela... | 08/07/2007 |
| 7253668 | Delay-locked loop with feedback compensation A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is adjusted to minimize phase error, multiple clock cycles may be required before the adjusted signal is fed back... | 08/07/2007 |
