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| Number | Title | Issue Date |
| 8188776 | Phase-locked loop circuit A phase-locked loop circuit includes a control loop including a frequency divider configured to frequency-divide an output clock and to control a frequency of the output clock according to a phase difference between a local clock and a phase-divided local clock; and... | 05/29/2012 |
| 8179174 | Fast phase locking system for automatically calibrated fractional-N PLL The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode... | 05/15/2012 |
| 8169241 | Proportional phase comparator and method for phase-aligning digital signals Embodiments of a proportional phase comparator and method for aligning digital signals are generally described herein. In some embodiments, circuitry to align digital signals comprises a proportional phase comparator that generates triangular-shaped pulses for appli... | 05/01/2012 |
| 8169242 | Programmable fine lock/unlock detection circuit An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also incl... | 05/01/2012 |
| 8164366 | Locked loops, bias generators, charge pumps and methods for generating control voltages Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator, such as a voltage controlled delay line, in a locked loop having a phase... | 04/24/2012 |
| 8159275 | Phase-locked loop and bias generator A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power ... | 04/17/2012 |
| 8149030 | Clock generator to reduce long term jitter A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clo... | 04/03/2012 |
| 8134392 | Phase locked loop A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency... | 03/13/2012 |
| 8134393 | Method and apparatus for correcting phase offset errors in a communication device A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and/or phase locked loop circuits is provided with a means for minimizing static phase/delay errors. An auto-tuning circuit and technique provide a measurement of static phase... | 03/13/2012 |
| 8130015 | Clock generating circuit, semiconductor device including the same, and data processing system To include a phase determining circuit that generates a first phase determination signal, a sampling circuit that samples the first phase determination signal and generates a second phase determination signal based on the sampled first phase determination signal, an... | 03/06/2012 |
| 8125253 | System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal an... | 02/28/2012 |
| 8125254 | Techniques for configuring multi-path feedback loops In some embodiments, a feedback loop circuit includes a phase detector, first and second charge pumps that are each coupled to receive an output signal of the phase detector, a first low pass filter, a second low pass filter coupled to an output of the second charge... | 02/28/2012 |
| 8125255 | PLL circuit Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a ... | 02/28/2012 |
| 8120395 | Use of data decisions for temporal placement of samplers A data receiver has a clock recovery and data sampling circuit. This has a fixed local oscillator for timing the data samples. A phase interpolator adjusts the phase of the clock signal in response to an early late detector which samples the waveform at the expected... | 02/21/2012 |
| 8120394 | Automatic frequency calibration circuit and automatic frequency calibration method An automatic frequency calibration circuit and an automatic frequency calibration method for a fractional-N frequency synthesizer are provided. In a calibration mode, a state machine adjusts a fractional part and an integer part of a division ratio of a frequency di... | 02/21/2012 |
| 8115527 | PLL apparatus There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified and a control voltage is supplied to a voltage-controlled oscillator ... | 02/14/2012 |
| 8115525 | Frequency synthesizer There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output ... | 02/14/2012 |
| 8115526 | PLL oscillator circuit Disclosed is a PLL oscillator circuit capable of examining an unlock state while being equipped with an auto retry function enabling automatic relock. In the PLL oscillator circuit, a MPU receives a lock detection signal from the PLL-IC that receives an external ref... | 02/14/2012 |
| 8111092 | Register with process, supply voltage and temperature variation independent propagation delay path A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to ... | 02/07/2012 |
| 8111093 | Power supply noise rejection in PLL or DLL circuits A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency loc... | 02/07/2012 |
| 8106691 | Phase adjustment circuit In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase ... | 01/31/2012 |
| 8106690 | Semiconductor integrated circuit device To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator is frequency-divided by a frequency divider, and is output as a first... | 01/31/2012 |
| 8102197 | Digital phase locked loop An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedba... | 01/24/2012 |
| 8102195 | Digital phase-locked loop circuit including a phase delay quantizer and method of use A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, h... | 01/24/2012 |
| 8102196 | Programmable dual phase-locked loop clock signal generator and conditioner A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module and an on-chip VCO with intra-PLL frequency doubling to provide a cl... | 01/24/2012 |
| 8085070 | Overclocking with phase selection A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency. ... | 12/27/2011 |
| 8076961 | Monitoring apparatus and computer-readable storage medium A monitoring apparatus monitors a system including an oscillator with a variable oscillation frequency. The monitoring apparatus has a transmitting unit to transmit an information collecting instruction for collecting state information of the system to the system at... | 12/13/2011 |
| 8076960 | Digital phase-locked loop with two-point modulation using an accumulator and a phase-to-digital converter A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit ... | 12/13/2011 |
| 8067965 | Clock and data recovery circuit with proportional path A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a curr... | 11/29/2011 |
| 8063677 | Phase locked loop and method for operating the same A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the interna... | 11/22/2011 |
| 8058915 | Digital phase-locked loop and digital phase-frequency detector thereof A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit,... | 11/15/2011 |
| 8058916 | Lockstep synchronization and maintenance A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first a... | 11/15/2011 |
| 8058914 | Generating multiple clock phases In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; ... | 11/15/2011 |
| 8054114 | Fractional-N phase-locked loop A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference f... | 11/08/2011 |
| 8049539 | Circuit with variation correction function A circuit with variation correction function is capable of obtaining an output characteristic near a desired value by suppressing variation of the output characteristic regardless of manufacturing characteristic variations of a component. An output signal different ... | 11/01/2011 |
| 8044692 | Level-restorer for supply-regulated PLL The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can ... | 10/25/2011 |
| 8035430 | Signal generator with output frequency greater than the oscillator frequency Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four s... | 10/11/2011 |
| 8022738 | Apparatus and method for detecting the loss of an input clock signal for a phase-locked loop An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and out... | 09/20/2011 |
| 8008955 | Semiconductor device There is provided a semiconductor device having a voltage-controlled oscillator outputting an output clock signal; N pieces of control units generating a frequency-divided clock signal by frequency-dividing the output clock signal, comparing a reference clock signal... | 08/30/2011 |
| 8004322 | Synchronization scheme with adaptive reference frequency correction The present invention relates to an apparatus and method for providing synchronization of an output signal to a synchronization information. The synchronization is accomplished by providing coupling of a correction control information that controls a signal generati... | 08/23/2011 |
