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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 8174297 | Multi-phase clock generation An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and seco... | 05/08/2012 |
| 8026747 | Apparatus and method for multi-phase clock generation An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and seco... | 09/27/2011 |
| 7932755 | Phase synchronization for wide area integrated circuits A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signa... | 04/26/2011 |
| 7667507 | Edge-timing adjustment circuit According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, ... | 02/23/2010 |
| 7336110 | Differential amplitude controlled sawtooth generator A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawto... | 02/26/2008 |
| 7327998 | System and method of providing a geographic view of nodes in a wireless network A geographic view rendering tool receives geographic location data for nodes in a wireless network and renders a geographic view displaying the nodes at their corresponding geographic locations. The geographic view may be displayed overlaying a digital map. The geog... | 02/05/2008 |
| 7319728 | Delay locked loop with frequency control A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry f... | 01/15/2008 |
| 7317775 | Switched deskew on arbitrary data A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first samplin... | 01/08/2008 |
| 7315162 | Reducing power consumption of electrical meters The invention contemplates an electrical power meter and method of operating the electrical power meter. The inventive power meter includes a power supply for converting alternating current (AC) voltage to a direct current (DC) voltage for powering the electronic co... | 01/01/2008 |
| 7312721 | Data collector for an automated meter reading system The invention includes an electronic utility meter, a data collector/meter and a method for communicating data in an automated meter reading system. The inventive method includes communicating data with a network and a first electronic utility meter, and communicati... | 12/25/2007 |
| 7310057 | Latch clock generation circuit and serial-parallel conversion circuit A serial-parallel conversion circuit in which power consumption is reduced is provided by using a latch clock generation circuit including multiple latch signal generation circuits which outputs a latch signal with a period of an integer multiple of that of a system... | 12/18/2007 |
| 7301375 | Off-chip driver circuit and data output circuit using the same An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip... | 11/27/2007 |
| 7301476 | Dynamic self-configuring metering network A dynamic self-configuring system for collecting metering data comprises a collector meter. The collector meter scans for meters that are operable to directly communicate with the collector and registers such meters as level one meters. The collector transmits instr... | 11/27/2007 |
| 7295053 | Delay-locked loop circuits A delay-locked loop (DLL) circuit comprises a voltage controlled delay line (VCDL) including a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number ... | 11/13/2007 |
| 7288969 | Zero clock delay metastability filtering circuit A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge ... | 10/30/2007 |
| 7274236 | Variable delay line with multiple hierarchy Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal, and has particular utility as the variable delay in a delay-locked l... | 09/25/2007 |
| 7262709 | System and method for efficient configuration in a fixed network automated meter reading system Meters are configured using either a program update method or a meter update method. In the program update method, meters associated with a specified configuration program are identified and configured with updated parameters. In the meter update method, a specified... | 08/28/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7245683 | System and methods of recovering a clock from NRZ data A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an i... | 07/17/2007 |
| 7239250 | System and method for improved transmission of meter data The system includes a number of first meters, which are typically battery powered transmit only devices. The system includes a number of two-way meters, which are operable to both transmit and receive data. The first meters transmit their data to the collector eithe... | 07/03/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7227350 | Bias technique for electric utility meter The invention contemplates an electrical power meter and method of operating the same, where the meter has electronic components (e.g., a power supply and a voltage sensing circuit) and receives alternating current (AC) voltage from an electrical power line. The inv... | 06/05/2007 |
| 7227795 | Data output circuit, data output method, and semiconductor memory device In a data output circuit, a data output method, and a semiconductor memory device, the data output circuit includes: an internal clock generation unit that delays an external clock signal by a first delay time to output an internal clock signal in response to the ex... | 06/05/2007 |
| 7219250 | Status indication detection and device and method A status indication detection apparatus comprises an input storage stage, an intermediate storage stage and an output storage stage. Status indications are input into the input register of the input stage and are shifted to the intermediate and to the output stage. ... | 05/15/2007 |
| 7200451 | Method for consistent on/off object to control radios and other interfaces In a method and system for controlling a device coupled to an information handling system, an object is defined to include a hardware and software component having a corresponding hardware operating state and a software operating state. The hardware component is ope... | 04/03/2007 |
| 7199629 | Circuit having delay locked loop for correcting off chip driver duty distortion A circuit comprises an off chip driver and a delay locked loop. The delay locked loop is configured to receive a clock signal and provide a first signal for compensating for a rising edge propagation delay through the off chip driver and a second signal for compensa... | 04/03/2007 |
| 7190200 | Delay locked loop capable of performing reliable locking operation A delay locked loop capable of performing a reliable locking operation is provided that includes a phase controller, which controls a phase of a reference clock signal in response to first and second phase control signals, and a phase detector, which compares the ph... | 03/13/2007 |
| 7187906 | Method and system for configurable qualification and registration in a fixed network automated meter reading system A dynamic self-configuring system for collecting metering data comprises a collector meter. The collector meter scans for meters that are operable to directly communicate with the collector and registers such meters as level one meters. The collector transmits instr... | 03/06/2007 |
| 7177380 | System and methods of recovering a clock from NRZ data A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an i... | 02/13/2007 |
| 7176807 | System for automatically enforcing a demand reset in a fixed network of electricity meters Methods and systems of enforcing a demand reset in a meter that communicates via a wireless network. When billing data is received by a server, it is accompanied by a demand reset counter. The counter is compared to a counter stored on the server. If they received c... | 02/13/2007 |
| 7170425 | System and method for creating multiple operating territories within a meter reading system The present invention enables multiple operating territories to be defined, named, and managed within a meter reading system. Each operating territory may correspond to a geographic sub-section of the meter reading system that is regulated by a particular regulatory... | 01/30/2007 |
| 7170325 | Circuit for controlling a delay time of input pulse and method of controlling the same Provided is directed to a circuit of controlling a pulse width and a method of controlling the same, which can remove failure possible to be generated during operations of a DRAM or a DDR in a high frequency by guaranteeing read and write operations of a stabilized ... | 01/30/2007 |
| 7164295 | Feedback control system and method A feedback control system and method thereof are provided. The feedback control method includes (a) comparing the level of a reference signal with the levels of first and second signals, (b) if the levels of the first and second signals are lower than the level of t... | 01/16/2007 |
| 7162000 | Delay locked loop synthesizer with multiple outputs and digital modulation A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multip... | 01/09/2007 |
| 7161400 | Phase synchronization for wide area integrated circuits A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signa... | 01/09/2007 |
| 7149145 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 12/12/2006 |
| 7145381 | Apparatus for controlling a boosted voltage and method of controlling a boosted voltage The apparatus for controlling a boosted voltage includes a voltage generating circuit and a control circuit. The voltage generating circuit is configured to generate a boosted voltage from an input voltage based on a control current, and the control circuit is confi... | 12/05/2006 |
| 7145373 | Frequency-controlled DLL bias A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitu... | 12/05/2006 |
| 7145474 | Dynamic self-configuring metering network A dynamic self-configuring system for collecting metering data comprises a collector meter. The collector meter scans for meters that are operable to directly communicate with the collector and registers such meters as level one meters. The collector transmits instr... | 12/05/2006 |
