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| Number | Title | Issue Date |
| 8125252 | Multi-phase signal generator and method Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One ... | 02/28/2012 |
| 8018257 | Clock divider and clock dividing method for a DLL circuit A clock divider for a DLL circuit reduces power consumption by reducing the number of times of performing phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers and a power-down controller ... | 09/13/2011 |
| 8008954 | Multi-phase signal generator and method Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock signals including those having 90, 180, 270 and 360 degrees phase difference with a first clock signal. One ... | 08/30/2011 |
| 7965116 | Timing adjustment circuit, solid-state image pickup element, and camera system A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a ... | 06/21/2011 |
| 7755402 | Calibration of separate delay effects for multiple data strobe signals Embodiments for positioning rising and/or filling edges of data strobe signals are disclosed. One example embodiment may comprise receiving a data signal, positioning an edge of a first delayed data strobe signal associated with the data signal by a first programmab... | 07/13/2010 |
| 7605620 | System and method to improve the efficiency of synchronous mirror delays and delay locked loops A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay ... | 10/20/2009 |
| 7443743 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 10/28/2008 |
| 7443742 | Memory arrangement and method for processing data A memory arrangement for processing data comprises a memory, an interface operatively coupled to the memory, a DLL circuit and at least one register device comprising a data input and a clock input. Read data is applied to the interface in response to a read access ... | 10/28/2008 |
| 7428286 | Duty cycle correction apparatus and method for use in a semiconductor memory device The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of current being consumed, and to a method thereof. The duty cycle correct... | 09/23/2008 |
| 7423462 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 09/09/2008 |
| 7423919 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 09/09/2008 |
| 7423464 | Phase and amplitude modulator The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to an input signal, a first variable delay device having its input coupl... | 09/09/2008 |
| 7421048 | System and method for multimedia delivery in a wireless environment A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing ... | 09/02/2008 |
| 7420430 | Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock sig... | 09/02/2008 |
| 7414444 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 08/19/2008 |
| 7398412 | Measure controlled delay with duty cycle control The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a dela... | 07/08/2008 |
| 7391246 | Digital high speed programmable delayed locked loop A digital high speed programmable delayed locked loop (DLL) includes a zero degree phase shift digital delay line, at least one intermediate phase shift digital delay line, a three hundred and sixty degree phase shift digital delay line, and a digital control module... | 06/24/2008 |
| 7375558 | Method and apparatus for pre-clocking A method and apparatus for pre-clocking have been disclosed. ... | 05/20/2008 |
| 7348823 | Delay circuit and delay synchronization loop device A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay uni... | 03/25/2008 |
| 7336752 | Wide frequency range delay locked loop A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and... | 02/26/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7324540 | Network protocol off-load engines The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines). ... | 01/29/2008 |
| 7319352 | Phase and amplitude modulator The invention relates to an apparatus for precise modulation of signal phase and signal delay, respectively, and signal amplitude, comprising a first fixed-delay device having its input coupled to an input signal, a first variable delay device having its input coupl... | 01/15/2008 |
| 7317343 | Pulse-generation circuit with multi-delay block and set-reset latches In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and r... | 01/08/2008 |
| 7315957 | Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selecte... | 01/01/2008 |
| 7301375 | Off-chip driver circuit and data output circuit using the same An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip... | 11/27/2007 |
| 7298188 | Timing adjustment circuit and memory controller A circuit for timing adjustment includes a PLL circuit configured to generate a phase-adjusted clock signal in response to phase comparison between an input clock signal and a delayed clock signal, a feedback path configured to delay the phase-adjusted clock signal ... | 11/20/2007 |
| 7288973 | Method and apparatus for fail-safe resynchronization with minimum latency A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 10/30/2007 |
| 7282952 | Level shift circuit, electro-optical device using the same, and electronic apparatus A level shift circuit includes a capacitor element that has one terminal to which a logic input signal having a first logic amplitude is input; a logic output circuit that includes a first logic inverting circuit having a first logic inversion level with respect to ... | 10/16/2007 |
| 7279944 | Clock signal generator with self-calibrating mode A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for... | 10/09/2007 |
| 7274238 | Digital circuit having delay circuit for adjustment of clock signal timing A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a puls... | 09/25/2007 |
| 7259599 | Semiconductor device In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signa... | 08/21/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7239575 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 07/03/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7236026 | Circuit for and method of generating a frequency aligned clock signal A circuit for generating a clock signal which is frequency aligned with a reference clock signal is disclosed. The circuit comprises a phase detector coupled to receive the reference clock signal and the generated clock signal. A frequency alignment circuit generate... | 06/26/2007 |
| 7236551 | Linear half-rate phase detector for clock recovery and method therefor There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and... | 06/26/2007 |
| 7230458 | Delta/sigma frequency discriminator Delta/sigma frequency discriminator (1) for converting a frequency (Fv) of an input signal into a digital output signal (C) comprising a frequency divider (8) which divides the input signal at a frequency dividing ratio which can be switched... | 06/12/2007 |
| 7228248 | Test apparatus, timing generator and program therefor There is provided a test apparatus including a PLL circuit for generating a strobe signal of which the timing is shifted according to a given delay control voltage, a variable delay circuit being provided divergently from a path connecting the PLL circuit and the ti... | 06/05/2007 |
