Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 8081020 | Delay-lock loop and method adapting itself to operate over a wide frequency range A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A... | 12/20/2011 |
| 7443743 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 10/28/2008 |
| 7436228 | Variable-bandwidth loop filter methods and apparatus Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor circuitries coupled to a capacitor. One of the resistor circuitries can be coup... | 10/14/2008 |
| 7433441 | System and method for adaptively deskewing parallel data signals relative to a clock A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality... | 10/07/2008 |
| 7423461 | Phase synchronous circuit An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. F... | 09/09/2008 |
| 7423919 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 09/09/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7352218 | DLL circuit and method of controlling the same A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is... | 04/01/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
| 7317343 | Pulse-generation circuit with multi-delay block and set-reset latches In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and r... | 01/08/2008 |
| 7296170 | Clock controller with clock source fail-safe logic A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast in... | 11/13/2007 |
| 7286625 | High-speed clock and data recovery circuit A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.1... | 10/23/2007 |
| 7284143 | System and method for reducing clock skew In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal a... | 10/16/2007 |
| 7279944 | Clock signal generator with self-calibrating mode A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for... | 10/09/2007 |
| 7263149 | Apparatus and method for generating a distributed clock signal The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a differen... | 08/28/2007 |
| 7259608 | System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock ... | 08/21/2007 |
| 7259599 | Semiconductor device In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signa... | 08/21/2007 |
| 7253671 | Apparatus and method for compensating for clock drift in downhole drilling components A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded num... | 08/07/2007 |
| 7253670 | Phase synchronization circuit and semiconductor integrated circuit A phase synchronization circuit comprises: a measurement delay line which includes a plurality of delay elements having different delay times and to which a first clock signal is inputted; a phase comparator line which includes a plurality of phase comparators in ac... | 08/07/2007 |
| 7253672 | System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled ... | 08/07/2007 |
| 7250798 | Synchronous clock generator including duty cycle correction A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer... | 07/31/2007 |
| 7227394 | Signal synchronizer system and method A signal synchronizer according to embodiments herein uses a delay register that receives a feedback signal. The delay register has many delay circuits, each of which are adapted to delay the feedback signal at different time intervals. A storage register made up of... | 06/05/2007 |
| 7224199 | Circuit and method for digital delay and circuits incorporating the same A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the fi... | 05/29/2007 |
| 7212598 | Data buffer-controlled digital clock regenerator A clock regeneration scheme for a digital communication receiver has a first-in, first-out (FIFO) storage buffer into which received data is clocked in accordance with an input clock signal and a data valid signal. A fixed fractional delay line is coupled to provide... | 05/01/2007 |
| 7212048 | Multiple phase detection for delay loops A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to ge... | 05/01/2007 |
| 7212054 | DLL with adjustable phase shift using processed control signal Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector... | 05/01/2007 |
| 7208989 | Synchronous clock generator including duty cycle correction A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer... | 04/24/2007 |
| 7170331 | Delay circuit A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output si... | 01/30/2007 |
| 7170963 | Clock recovery method by phase selection The present invention demonstrates a method and circuit where a plurality of phase clocks from a “frequency lock only” PLL are used to sample an input clock CLKIN. This results in a series of signals from which the phase clock most in synchronization with CLKIN ... | 01/30/2007 |
| 7167935 | Accessory control interface Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave de... | 01/23/2007 |
| 7162000 | Delay locked loop synthesizer with multiple outputs and digital modulation A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multip... | 01/09/2007 |
| 7161408 | Semiconductor integrated circuit device and microcomputer A semiconductor integrated circuit includes a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS trans... | 01/09/2007 |
| 7148733 | Variable delay circuit with faster delay data update Delays induced to leading and trailing edges of an input pulse train are updated faster than before. First and second delay paths receive delay data for inducing delays to leading edges and/or trailing edges of an input pulse train. An OR circuit combines the output... | 12/12/2006 |
| 7142033 | Differential clocking scheme in an integrated circuit having digital multiplexers A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differentia... | 11/28/2006 |
| 7138837 | Digital phase locked loop circuitry and methods Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal.... | 11/21/2006 |
| 7124314 | Method and apparatus for fine tuning clock signals of an integrated circuit An IC including skew-programmable clock buffers, fixed skew logic circuit, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. ... | 10/17/2006 |
| 7120215 | Apparatus and method for on-chip jitter measurement A jitter measurement circuit is described comprising delay elements arranged in a serially-connected chain, and first and second sets of circuitry. Each delay elements has an associated delay, an input and an output that produces a delayed version of the signal at t... | 10/10/2006 |
| 7119593 | Delayed signal generation circuits and methods Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked ... | 10/10/2006 |
| 7116141 | Frequency-doubling delay locked loop A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs ... | 10/03/2006 |
