Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 8093933 | Method of fast tracking and jitter improvement in asynchronous sample rate conversion A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and... | 01/10/2012 |
| 7863952 | Method and circuit for controlling clock frequency of an electronic circuit with noise mitigation A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use o... | 01/04/2011 |
| 7567100 | Input clock detection circuit for powering down a PLL-based system An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and out... | 07/28/2009 |
| 7428286 | Duty cycle correction apparatus and method for use in a semiconductor memory device The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of current being consumed, and to a method thereof. The duty cycle correct... | 09/23/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7375553 | Clock tree network in a field programmable gate array A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elemen... | 05/20/2008 |
| 7372759 | Power supply control circuit and controlling method thereof The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory dev... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7352253 | Oscillator circuit with tuneable signal delay means The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit fu... | 04/01/2008 |
| 7336752 | Wide frequency range delay locked loop A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and... | 02/26/2008 |
| 7332947 | Method and apparatus for distorting duty cycle of a clock An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described. ... | 02/19/2008 |
| 7296173 | Semiconductor integrated circuit A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input te... | 11/13/2007 |
| 7284173 | Built-in self-test circuit for phase locked loops, test method and computer program product therefor A built-in self-test circuit for phase locked loops includes a measurement circuit for measuring outputs of the phase locked loops, and receiving as inputs a plurality of external test signals. At least one module includes a scan chain for storing the test signals f... | 10/16/2007 |
| 7259599 | Semiconductor device In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signa... | 08/21/2007 |
| 7253669 | High resolution digital loop circuit A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum reso... | 08/07/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7194670 | Command multiplier for built-in-self-test Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alo... | 03/20/2007 |
| 7170323 | Delay locked loop harmonic detector and associated method We describe and claim a delay locked loop harmonic detector and associated method. A delay locked loop includes a detection circuit to generate a detection signal responsive to an input clock and a control circuit to synchronize the delay locked loop to a fundamenta... | 01/30/2007 |
| 7162001 | Charge pump with transient current correction An improved charge pump used in a phase-locked loop includes transient current correction capability by adding a canceling capacitance for each parasitic capacitance associated with a switching device in a charge pump. For each transient current component flowing th... | 01/09/2007 |
| 7159134 | Method and apparatus for clock and power control in wireless systems A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal ... | 01/02/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7151399 | System and method for generating multiple clock signals A technique for generating multiple clock signals using a frequency generator for generating a common clock signal. A first digital divider and multiplier receives the common clock signal and produces a first clock signal. A second digital divider and multiplier rec... | 12/19/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7132867 | High resolution digital loop circuit A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum reso... | 11/07/2006 |
| 7109765 | Programmable phase shift circuitry A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability f... | 09/19/2006 |
| 7106110 | Clock dithering system and method during frequency scaling A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for... | 09/12/2006 |
| 7088796 | Phase detector customized for clock synthesis unit A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic... | 08/08/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7076014 | Precise synchronization of distributed systems A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of t... | 07/11/2006 |
| 7076679 | System and method for synchronizing multiple variable-frequency clock generators In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency cl... | 07/11/2006 |
| 7061223 | PLL manufacturing test apparatus A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controll... | 06/13/2006 |
| 7049846 | Clock tree network in a field programmable gate array A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elemen... | 05/23/2006 |
| 7046042 | Phase detector A phase detector includes a first flip-flop responsive to a reference clock signal, a first inverter responsive to an output of the first flip-flop, a second flip-flop responsive to a feedback clock signal, a second inverter responsive to an output of the second fli... | 05/16/2006 |
| 7027548 | Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay... | 04/11/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 7007186 | Systems and methods for synchronizing a signal across multiple clock domains in an integrated circuit An integrated circuit configured to capture an input signal to produce an output signal. The input signal is synchronized with a first clock signal. The output signal is synchronized with a second clock signal having a second frequency different from a first frequen... | 02/28/2006 |
| 7005899 | Frequency division/multiplication with jitter minimization A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the inventio... | 02/28/2006 |
| 6998886 | Apparatus and method for PLL with equalizing pulse removal A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circ... | 02/14/2006 |
| 6987405 | Apparatus and method for generating multi-phase signals with digitally controlled trim capacitors An apparatus for generating multi-phase signals includes a delay chain to produce multi-phase signals, a slow boundary signal, and a fast boundary signal. An array of trim capacitors is connected to the delay chain. A timing control window circuit produces a control... | 01/17/2006 |
| 6963234 | Phase regulating circuit with a time-delay element A phase-locked loop with a delay element (DLL) is described which is essentially characterized in that the delay element (3) has a chain of a number n delay units (33n), the outputs (34n) of which are fed to a locking monitoring ci... | 11/08/2005 |
