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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 8183899 | Semiconductor integrated circuit and control method for clock signal synchronization There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second... | 05/22/2012 |
| 8154326 | Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback c... | 04/10/2012 |
| 8058913 | DLL-based multiphase clock generator The present invention relates to a delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from an input clock signal using a voltage controlled delay line including a plurality of dummy cells. The delay-locked loop-based m... | 11/15/2011 |
| 7911246 | DLL circuit and method of controlling the same A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization ... | 03/22/2011 |
| 7777539 | Delay adjusting circuit and control method of the same A delay adjusting circuit including a delay part in which delay elements of n+1 (n≧2) stages are connected to each other in series, a first phase comparator for detecting whether a first edge that is a transition edge of a signal of an n−1-th stage of the delay ... | 08/17/2010 |
| 7755401 | Semiconductor device including DLL circuit, and data processing system A DLL circuit includes: a phase determining circuit that compares phases of respective rising edges of CK and LCLK to generate a determining signal R-U/D; a phase determining circuit that compares phases of respective falling edges of CK and LCLK to generate a deter... | 07/13/2010 |
| 7728636 | Clock signal synchronizing device with inherent duty-cycle correction capability One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to corre... | 06/01/2010 |
| 7692459 | High resolution delay adjustor A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a f... | 04/06/2010 |
| 7671644 | Process insensitive delay line A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase de... | 03/02/2010 |
| 7583115 | Delay line off-state control with power reduction A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop com... | 09/01/2009 |
| 7443216 | Trimmable delay locked loop circuitry with improved initialization characteristics Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay li... | 10/28/2008 |
| 7436230 | Delay locked loop with improved jitter and clock delay compensating method thereof A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The dela... | 10/14/2008 |
| 7433441 | System and method for adaptively deskewing parallel data signals relative to a clock A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality... | 10/07/2008 |
| 7428286 | Duty cycle correction apparatus and method for use in a semiconductor memory device The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of current being consumed, and to a method thereof. The duty cycle correct... | 09/23/2008 |
| 7425858 | Delay line periodically operable in a closed loop A delay line is periodically configured into a delay-locked loop for calibration purposes. That is, the delay line is operated in an open loop mode during a first time period in which a signal, such as an aperiodic signal, is the input signal into the delay line. Pe... | 09/16/2008 |
| 7414445 | Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the pha... | 08/19/2008 |
| 7403053 | Power supply dependent delay compensation An integrated circuit compensates for power supply voltage dependent delay using a clock circuit that is responsive to a power supply voltage measuring circuit. The clock circuit modifies a phase relationship based on a measured power supply voltage value. ... | 07/22/2008 |
| 7400181 | Method and apparatus for delay line control using receive data Methods and apparatus are provided for delay line control using receive data. A delay in a Delay-Locked-Loop circuit is controlled by obtaining a plurality of samples of one or more received signals for each unit interval; determining a data eye width in the one or ... | 07/15/2008 |
| 7397880 | Synchronization circuit and synchronization method In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the ph... | 07/08/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7391244 | Delay-locked loop This invention relates to a delay locked loop comprising a line of delay cells (R1, R2, . . . , Rn) mounted in series, the delay signal output by the loop being output from the output of one of the delay cells, the input of the delay cells line being c... | 06/24/2008 |
| 7391245 | Delay locked loop and method for setting a delay chain A delay locked loop includes a delay chain that contains a plurality of series-connected delay cells, a phase detector arrangement that contains a plurality of phase detector cells and a control unit. The delay locked loop delays an input signal by a delay time via ... | 06/24/2008 |
| 7385428 | Digital delay locked loop capable of correcting duty cycle and its method An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal ... | 06/10/2008 |
| 7379521 | Delay circuit with timing adjustment function In a phase locked loop circuit, a phase comparator compares the phase of input clock and that of output clock, and provides a control signal as the comparison result. A charge pump circuit includes a clamp circuit, and based on the control signal, provides a control... | 05/27/2008 |
| 7378888 | Delay-locked loop circuit The delay of delay circuit 10 is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal φin when transition is made from the stop mode to the DLL mode are excluded from the object detected by phase detector 20 | 05/27/2008 |
| 7375558 | Method and apparatus for pre-clocking A method and apparatus for pre-clocking have been disclosed. ... | 05/20/2008 |
| 7372310 | Digital frequency-multiplying DLLs Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of uni... | 05/13/2008 |
| 7372311 | Delay locked loop for controlling duty rate of clock There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty... | 05/13/2008 |
| 7372331 | Receiver circuit A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data signal and a reference signal into the receiver circuit, a multistage input amplifier circuit which comprises... | 05/13/2008 |
| 7368965 | Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clo... | 05/06/2008 |
| 7369457 | Semiconductor memory device A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense ... | 05/06/2008 |
| 7368963 | Delay locked loop for use in semiconductor memory device and method thereof A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locke... | 05/06/2008 |
| 7366048 | Bulk bias voltage level detector in semiconductor memory device There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a sem... | 04/29/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7365583 | Delay locked loop for high speed semiconductor memory device A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputt... | 04/29/2008 |
| 7362303 | Device and method of driving light source in display devices A device for driving a light source in an image display device includes input terminals to receive a horizontal synchronization signal and a control signal, an oscillator to generate a reference signal having a frequency, a controller to modulate the reference signa... | 04/22/2008 |
| 7358784 | Delay locked loop A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle c... | 04/15/2008 |
| 7355464 | Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the tec... | 04/08/2008 |
| 7355380 | Methods and apparatus for testing delay locked loops and clock skew According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay in... | 04/08/2008 |
| 7352253 | Oscillator circuit with tuneable signal delay means The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit fu... | 04/01/2008 |
