Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
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| Number | Title | Issue Date |
| 7986175 | Spread spectrum control PLL circuit and its start-up method A calibration circuit (19) adjusts at least one of one of a charging current of a charge pump circuit (12) and a capacitance value of a filter capacitor in a loop filter circuit (13) and a gain of a voltage controlled oscillator (14), dep... | 07/26/2011 |
| 7965115 | Soft reference switch for phase locked loop A phase locked loop includes a digital controlled oscillator and a number of phase detectors, each having a first input connected to a reference source and a second input coupled to the output of the digital controlled oscillator, and an output for producing a phase... | 06/21/2011 |
| 7902886 | Multiple reference phase locked loop A multi reference phase locked loop (MPLL) generates a high speed clock frequency and phase locks it to a lowest common reference frequency derived from a selected one of at least two reference clocks. One of the reference clocks is a system reference clock in a FBD... | 03/08/2011 |
| 7884654 | Circuit arrangement and method for controlling an electrical load A circuit arrangement (10) for driving an electrical load (2) comprises an input (11) for feeding a power-supply voltage (Vs) with an AC component and an output (13) for providing an output signal (Sout) for driving a connectable electric... | 02/08/2011 |
| 7764092 | Phase locked loop and phase locking method A phase locked loop includes a charge pump, a voltage-current converter, and a current controlled oscillator. The charge pump generates a pump current based on a bias voltage and a phase difference detection signal, in which the pump current is for adjusting a contr... | 07/27/2010 |
| 7759990 | Clock switching circuit A clock switching circuit comprises PLL circuits into which external clocks CLKT, CLKB are respectively input, a multiplexer for selecting and outputting either an output PLB of one PLL circuit or an inverted signal of an output PLT of the other PLL circuit, and a c... | 07/20/2010 |
| 7701267 | Semiconductor device including phase detector A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination sig... | 04/20/2010 |
| 7595670 | Electronic device and method for on chip skew measurement The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the o... | 09/29/2009 |
| 7541848 | PLL circuit Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a... | 06/02/2009 |
| 7535270 | Semiconductor memory device A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The del... | 05/19/2009 |
| 7501865 | Methods and systems for a digital frequency locked loop for multi-frequency clocking of a multi-core processor A method and systems for a digital frequency locked loop in a multi-core processor are provided. The method includes applying a dither modulation signal at a dither modulation frequency to modulate an output frequency to provide a clock signal to a core of the multi... | 03/10/2009 |
| 7443215 | Methods and apparatus to increase the resolution of a clock synthesis circuit that uses feedback interpolation A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. ... | 10/28/2008 |
| 7443742 | Memory arrangement and method for processing data A memory arrangement for processing data comprises a memory, an interface operatively coupled to the memory, a DLL circuit and at least one register device comprising a data input and a clock input. Read data is applied to the interface in response to a read access ... | 10/28/2008 |
| 7443213 | Staged locking of two phase locked loops Data synchronization is achieved in devices which transmit and/or receive audio and/or video data through the staged locking of phase locked loops. According to an exemplary embodiment, a transmitter includes a serial data source. An encoder provides encoded data an... | 10/28/2008 |
| 7443214 | PLL circuit and frequency setting circuit using the same Disclosed is a PLL circuit in which an AC signal with a predetermined frequency is supplied as an input signal to a phase shifter comprising an OTA and a capacitor, and a phase comparator that receives the input signal to the phase shifter and an output signal from ... | 10/28/2008 |
| 7440518 | Phase-locked loop circuit A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (uDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a ... | 10/21/2008 |
| 7436229 | Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. ... | 10/14/2008 |
| 7436227 | Dual loop architecture useful for a programmable clock source and clock multiplier applications A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit... | 10/14/2008 |
| 7432749 | Circuit and method for improving frequency range in a phase locked loop A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a... | 10/07/2008 |
| 7430265 | Circuit arrangement provided with a phase-locked loop and transmitter-receiver with said circuit arrangement The invention specifies a circuit arrangement with a phase locked loop (1), which can be used as a mobile radio transmitter, in particular. The reference frequency for the PLL (1), which is provided by means of the source (3), is multiplied by a... | 09/30/2008 |
| 7425852 | Phase-locked loop The present invention relates to a phase-locked loop for frequency synthesis, which has a memory for a control value for the controllable oscillator of the phase-locked loop, which is connectable via a first switch to the control input of the controllable oscillator... | 09/16/2008 |
| 7421053 | Fast clock acquisition enable method using phase stir injection to PLL for burst mode optical receivers Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to loc... | 09/02/2008 |
| 7412019 | Spread spectrum clock generator A spread spectrum clock generator comprising a phase-locked loop circuit and a modulation circuit. The phase-locked loop circuit receives a reference signal at a reference frequency and outputs an output signal at an output frequency periodically varying in a range ... | 08/12/2008 |
| 7405628 | Technique for switching between input clocks in a phase-locked loop A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation si... | 07/29/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7382169 | Systems and methods for reducing static phase error In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feed... | 06/03/2008 |
| 7379005 | Apparatus and method for spectrally shaping a reference clock signal Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digita... | 05/27/2008 |
| 7375563 | Duty cycle correction using input clock and feedback clock of phase-locked-loop (PLL) A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) of the PLL drives a feedback ... | 05/20/2008 |
| 7373574 | Semiconductor testing apparatus and method of testing semiconductor A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison s... | 05/13/2008 |
| 7368962 | Clock supply device Each clock supply unit comprises an inter-unit synchronization portion which operates when the clock supply unit is acting as a standby unit, using a clock signal from a DPLL of a unit which is active as reference, to apply a predetermined phase difference to the ou... | 05/06/2008 |
| 7368946 | Level-shifting pass gate multiplexer The present invention incorporates level-shifting functions within a multiplexer circuit that may be implemented in IC devices having low and high voltage domains. The multiplexer circuit utilizes pseudo-differential multiplexing architectures and employs level-shif... | 05/06/2008 |
| 7365797 | Display synchronization signal generation apparatus in digital broadcast receiver and decoder A display synchronization signal generation apparatus and method is provided which makes it possible to display a stable image irrespective of changes in transmission speed of a received digital broadcast signal by generating a synchronization signal of an image to ... | 04/29/2008 |
| 7365580 | System and method for jitter control A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of the phase rotator are controlled by a delta-sigma modulator to provide ... | 04/29/2008 |
| 7362151 | Timing circuits with improved power supply jitter isolation technical background In accordance with the invention, feed forward compensation of jitter induced by power supply noise is incorporated into the negative feedback control loop of a timing synchronization circuit, such as a phase locked loop or delay locked loop. More particularly, the ... | 04/22/2008 |
| 7358783 | Voltage, temperature, and process independent programmable phase shift for PLL A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability f... | 04/15/2008 |
| 7355483 | System and method for mitigating phase pulling in a multiple frequency source system A method for mitigating phase pulling in multiple frequency source system includes generating a first signal, the first signal referred to as an existing signal operating at an existing frequency point, the existing signal having a predefined pulling bandwidth aroun... | 04/08/2008 |
| 7355922 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and ... | 04/08/2008 |
| 7352222 | Clock generator with programmable non-overlapping-clock-edge capability A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on... | 04/01/2008 |
| 7352218 | DLL circuit and method of controlling the same A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is... | 04/01/2008 |
| 7353009 | Combined transmitter A combined transmission unit for TMDS signals and LVDS signals. First (LVDS) and second (TMDS) transmission units are both coupled to a first set of input terminals. A switching controller, according to a mode selection signal, enables the first transmission unit to... | 04/01/2008 |
