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| Number | Title | Issue Date |
| 7977983 | Device having synchronizing capabilities A method and a device having synchronizing capabilities, the device includes; (i) a first circuit that is adapted to receive a first clock signal; (ii) a second circuit that is adapted to receive a second clock signal; wherein the first and second clock signals and ... | 07/12/2011 |
| 7911245 | Multi-phase signal generator and method A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals including those having 90, 180, 270 and 360 degrees phase difference with a first signal. The rising edge ... | 03/22/2011 |
| 7567099 | Filterless digital frequency locked loop A frequency and/or phase locked loop architecture that eliminates the loop filter generally required in conventional phase locked loops, and which may be implemented in digital logic, for example, as a field programmable gate array. In one example, a frequency/phase... | 07/28/2009 |
| 7443743 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 10/28/2008 |
| 7423919 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 09/09/2008 |
| 7421048 | System and method for multimedia delivery in a wireless environment A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing ... | 09/02/2008 |
| 7363557 | System for at-speed automated testing of high serial pin count multiple gigabit per second devices A system performs automated at-speed testing of a plurality of devices that generate serial data signals having multiple gigabit per second baud rates. The system includes a test head including a device interface board (DIB), the DIB having a device under test holdi... | 04/22/2008 |
| 7355483 | System and method for mitigating phase pulling in a multiple frequency source system A method for mitigating phase pulling in multiple frequency source system includes generating a first signal, the first signal referred to as an existing signal operating at an existing frequency point, the existing signal having a predefined pulling bandwidth aroun... | 04/08/2008 |
| 7334073 | Method of and apparatus for interfacing buses operating at different speeds The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined pe... | 02/19/2008 |
| 7324540 | Network protocol off-load engines The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines). ... | 01/29/2008 |
| 7319345 | Wide-range multi-phase clock generator A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respe... | 01/15/2008 |
| 7288973 | Method and apparatus for fail-safe resynchronization with minimum latency A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and v... | 10/30/2007 |
| 7276942 | Method for configurably enabling pulse clock generation for multiple signaling modes A method and a system for configurably generating enabling pulse clocks are disclosed herein. In various embodiments, enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse ... | 10/02/2007 |
| 7271545 | Ballast and igniter for a lamp having larger storage capacitor than charge pump capacitor A ballast according to the present invention operates in an ignition state, a warm-up state, and a steady state for igniting and powering a lamp. The ballast comprises an igniter that ignites the lamp during the ignition state and a switching power inverter, for exa... | 09/18/2007 |
| 7262833 | Circuit for addressing a memory A circuit is proposed which has a memory to which input data can be written at different write addresses with a first clock rate and from which output data can be read at different read addresses with a second clock rate. The memory can be fed a write reset pulse th... | 08/28/2007 |
| 7259599 | Semiconductor device In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signa... | 08/21/2007 |
| 7260753 | Methods and apparatus for providing test access to asynchronous circuits and systems Methods and apparatus are described for providing test access by synchronous test equipment to an asynchronous circuit. Synchronous-to-asynchronous (S2A) conversion circuitry is operable to receive synchronous input data serially from the synchronous test equipment ... | 08/21/2007 |
| 7257728 | Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-o... | 08/14/2007 |
| 7256635 | Low lock time delay locked loops using time cycle suppressor The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppr... | 08/14/2007 |
| 7253671 | Apparatus and method for compensating for clock drift in downhole drilling components A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded num... | 08/07/2007 |
| 7248123 | Phase locked loop with floating capacitor boost circuit Charge from a charge pump of a PLL is dumped to a loop filter of the PLL. The dumped charge is temporarily stored in a capacitor, between the charge pump and the loop filter. A voltage of the capacitor is shifted, while temporarily storing the dumped charge. Other e... | 07/24/2007 |
| 7236060 | Electronic pulse generator and oscillator Distributed traveling wave oscillator circuitry is disclosed. The oscillator circuitry includes a signal path, a plurality of active switching means, and a direction promoting means. The signal path is formed from a pair of adjacent conductors and exhibits endless e... | 06/26/2007 |
| 7237053 | Clock switching circuit for a hot plug One aspect of the present invention is a clock switching circuit for switching between asynchronous first clock and second clock when connecting or disconnecting an interface cable having a hot-plug function. The clock switching circuit includes a first group of fli... | 06/26/2007 |
| 7231008 | Fast locking clock and data recovery unit A method of synchronizing a transmitter and a receiver, comprising: receiving a transmitted serial data stream. Creating an N-bit data sample from the serial data stream. Decoding the N-bit data sample by a ring decoding technique. The ring decoding technique compri... | 06/12/2007 |
| 7218180 | Low noise oscillator A low noise oscillator constructed using a rotary traveling wave oscillator. The conductors of the rotary traveling wave oscillator provide at any tap position a pair of oppositely phased oscillations and these oscillations have slightly different phases at position... | 05/15/2007 |
| 7209065 | Rotary flash ADC A system and method for converting an analog signal to a digital signal is disclosed. The system includes a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit, an integrator and a time-to-digital converter. The multiphase oscillator has ... | 04/24/2007 |
| 7180332 | Clock synchronization circuit A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where ... | 02/20/2007 |
| 7164296 | Runt-pulse-eliminating multiplexer circuit A multiplexer circuit for selecting one of first and second input signals based on a first input select signal includes a multiplexer, a control circuit and an enable buffer. The multiplexer selects one of the first and second input signals based on a second input s... | 01/16/2007 |
| 7165184 | Transferring data between differently clocked busses A method of asynchronously transferring data from a low speed bus to a high speed bus, comprises latching data at a first predetermined instant in a cycle of the clock frequency of the high speed bus, latching data at a second predetermined instant in the same cycle... | 01/16/2007 |
| 7149145 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 12/12/2006 |
| 7146587 | Scalable logic self-test configuration for multiple chips A scalable LBIST control structure provides for testing of multiple independent clock domains within a chip and/or across multiple chips. The LBIST control structure sequences all clock domains through each step of the LBIST sequence synchronously, allowing multiple... | 12/05/2006 |
| 7123071 | Method and device for producing delayed signals In order to generate an output signal delayed compared to an input signal and with a defined mark-to-space ratio, it is useful to produce at least first and second intermediate signals delayed differently with respect to the input signal and to combine them to form ... | 10/17/2006 |
| 7098709 | Spread-spectrum clock generator This invention provides a clock generator which is capable of improving modulation accuracy without accompanying an increase in consumption current by steady current when spectrum spread of a clock signal is executed. The phase balanced voltage Vf to be inputted to ... | 08/29/2006 |
| 7082547 | Data signal processing method and data processor implementing independent and asynchronous system and data clocks A data clock for use in data communication between the connected processors and a system clock for use in data processing within the own processor are made independent and asynchronous in clock rate and adjustment between the two clocks is performed by an enable cre... | 07/25/2006 |
| 7081777 | Multiple-phase switching circuit A multiple-phase switching circuit includes an alternative signal generator for generating a plurality of alternative signals according to a switching signal, and a multiplexer for receiving a plurality of clock signals and outputting a target clock signal according... | 07/25/2006 |
| 7065668 | Apparatus for selecting and outputting either a first clock signal or a second clock signal By using a CR oscillating circuit and a PLL oscillating circuit selectively, these two oscillating circuits are used as a high frequency, low power consumption, short waiting time for stable oscillation, and low operating voltage oscillating circuit. ... | 06/20/2006 |
| 7061286 | Synchronization between low frequency and high frequency digital signals A synchronization circuit for synchronizing low frequency digital circuitry and high frequency digital circuitry. The synchronization circuit produces an ordered series of clocks from the high-frequency digital clock. The clocks have a deterministic time relationshi... | 06/13/2006 |
| 7046047 | Clock switching circuit A clock switching circuit capable of preventing occurrence of hazards in an output clock signal at a time of clock switching, regardless of the frequency ratio of input clock signals. At a time of switching to a second input clock signal CLKIN_B from a first input c... | 05/16/2006 |
| 7038506 | Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system A digital logic system includes a reset input for receiving a reset signal, and a clock input for receiving an externally generated main clock signal. An ancillary clock generator generates an ancillary clock signal. A clock selection multiplexer has a first input f... | 05/02/2006 |
| 7039146 | Method and interface for glitch-free clock switching A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock... | 05/02/2006 |
